Dalsa Corporation

Teledyne Dalsa, Inc.

Eric Charles Fox

Douglas Raymond Dykaar

Charles Russell Smith

Nixon O

Jaroslav Hynecek

Gareth Pryce Weale

Michael George Farrier

Michael Miethig

Matthias Sonder

Binqiao Li

An improved complementary metal oxide semiconductor image sensor for time delay and integration imaging is provided that utilizes rolling shutter pixels. Columns of rolling shutter pixels in the CMOS image array are provided with a space between adjacent pixels to provide synchronization with movement of the subject in the along track direction. Preferably, the physical offset between the pixels is 1/Nth of a pixel pitch for a column having N rows.

CMOS TDI image sensor with rolling shutter pixels

A sensor includes control circuitry and a pixel. The pixel includes a photo site, a first storage node and a second storage node. The control circuitry causes the pixel to transfer a first collected signal from the photo site to the first storage node during a first period, to transfer a second collected signal from the photo site to the second storage node during a second period that follows the first period, and to transfer the first and second collected signals out of the pixel during a third period that follows the second period.

Dual storage node pixel for CMOS sensor

A pixel includes five transistors, a photodetector and a storage node. A first transistor is coupled between the photodetector and the storage node. A second transistor includes a second transistor source and a second transistor drain. The second transistor source is coupled to the storage node. The second transistor drain is coupled to an output drain voltage. A third transistor includes a third transistor drain. The third transistor is coupled between the photodetector and a pixel reset voltage. The third transistor drain is coupled to the pixel reset voltage. The pixel reset voltage is different than the output drain voltage.

Five transistor CMOS pixel

A column slice of a CMOS TDI sensor includes a column bus, a column of pixels, plural first switches, a column of accumulators, plural second switches, plural third switches and output bus. Each of the plural first switches is coupled between the column bus and a corresponding pixel of the column of pixels, and each of the plural second switches is coupled between the column bus and a corresponding accumulator of the column of accumulators. In operation, only one switch at a time of plural first switches is 'on' to connect the voltage signal from a corresponding pixel to the column bus while all remaining plural first switches are 'off' to isolate the column bus from all remaining pixels. Only one of the plural second switches is &#x201c;on&#x201d; to connect the signal on the column bus to an accumulator while all remaining plural second switches are &#x201c;off&#x201d; to isolate the bus from all remaining accumulators. A main control circuit includes first and second shift registers to control the plural first and second switches to couple a signal from each pixel of the column of pixels into a corresponding accumulator of the column of accumulators while updating the accumulator until signals from all pixels have been transferred into corresponding accumulators. After this update cycle, an accumulated signal from the one accumulator that is currently addressed by a third shift register is read to the output. Then, the first and third shift registers are incremented. A new update cycle begins when a point in a moving image focused on the column slice crosses a pixel boundary. The same pattern repeats continuously. Valid TDI data is produced at the output after a number of full cycles of the transfer of pixels signals to the accumulators has been complete, the number being equal to the number of pixels.

CMOS TDI image sensor

A method of sensing radiation in a pixel includes applying a transfer clock signal, applying a pixel reset clock signal, and applying a pixel reset voltage. The applying a transfer clock signal applies the transfer clock signal to a gate electrode of a transfer gate transistor. The applying a pixel reset clock signal applies the pixel reset clock signal to a gate electrode of the pixel reset transistor. The applying a pixel reset voltage applies the pixel reset voltage to a drain of the pixel reset transistor. The method further includes switching the transfer clock signal to a high state, switching the pixel reset clock signal to a high state, switching the pixel reset voltage to a low state, switching the pixel reset voltage to a high state, and switching the pixel reset clock signal to a low state at a beginning of an integration cycle.

A sensor formed in a substrate of a first conductivity type in a first concentration to express a first intrinsic potential includes CMOS circuitry to control the sensor, a first well of the first conductivity type in a second concentration (greater than the first concentration) formed in the substrate to express a second intrinsic potential, and a photodiode region of a second conductivity type formed in the first well. The first and second intrinsic potentials induce a field between the substrate and the first well that repels photo generated charge from drifting from the substrate into the first well. Alternatively, a sensor formed in a substrate of a first conductivity type includes CMOS circuitry to control the sensor, a first well of a second conductivity type formed in the substrate, a second well of the first conductivity type formed in the first well, and a photodiode region of the second conductivity type formed in the second well.

Isolated photodiode

A pixel includes five transistors, a pinned photodiode and a storage node. A first transistor is coupled between the pinned photodiode and the storage node. A second transistor is coupled between the storage node and an output drain voltage. A third transistor is coupled between the pinned photodiode and a pixel reset voltage. The pixel reset voltage is different than the output drain voltage.

Pinned photodiode five transistor pixel

A single phase charge-couple device (CCD) transfer device in a substrate of a first conductivity type. The device includes a gated region and a photo-diode region. The gated region includes a gated part and a gate electrode insulatively spaced over the gated part. The photo-diode region includes first, second, and third diode sub-regions. The second diode sub-region is formed of a second conductivity type; the third diode sub-region is formed of the first conductivity type in the second diode sub-region; and the first diode sub-region is formed of the first conductivity type in the second diode sub-region. The first and third diode sub-regions contain different dopant concentrations. The gated part is either a buried channel gated part or a surface channel gated part. The buried channel gated part includes a channel of the second conductivity type and a first gated sub-region formed in the channel.

CMOS compatible single phase CCD charge transfer device

A pixel includes a photon detecting element coupled between a node and a ground, a transistor structure coupled between the node and a first predetermined voltage to provide a logarithmic response region, and a reset transistor coupled between the node and a second predetermined voltage to provide a linear response region where the second predetermined voltage is greater than the first predetermined voltage.

Sensor pixel with linear and logarithmic response

a pixel is formed in a substrate having a first conductivity type, the pixel being coupled to a register for output. The pixel includes a pixel channel of a second conductivity type formed in the substrate, a transfer gate electrode, a storage gate electrode and a photodiode. The pixel channel includes a transfer portion at a first end of the pixel channel proximal to the register, a diode portion at a second end distal to the register and a storage portion between the transfer portion and the diode portion. The transfer gate electrode is insulatively spaced over the transfer portion, and the storage gate electrode is insulatively spaced over the storage portion. The diode is formed within the diode portion using the storage gate electrode as a mask.

Pixel with buried channel spill well and transfer gate

A fast frame interline transfer charge coupled device imaging sensor includes an imaging section and an storage section. The imaging section includes a plurality of interline transfer registers, each interline transfer register containing a plurality of interline register elements. The imaging section further includes an interline clocking structure, the interline clocking structure including polycrystalline silicon buss lines used as gate electrodes, the polycrystalline silicon buss lines being connected to a metal strapping network, the interline clocking structure causing charge to be transferred between interline register elements of each interline transfer register based on interline clocking signals. The storage section is coupled to the imaging section. The storage section includes a plurality of storage registers, each storage register containing a plurality of storage register elements. The storage section further includes a storage discharge structure and a storage clocking structure. Each storage register element of the storage registers is selectively coupleable through the storage discharge structure to a storage drain. The storage clocking structure has first and second clocking structure parts, the first clocking structure part corresponding to first storage register elements coupled to respective interline registers. The first clocking structure part is coupled to the interline clocking structure so as to cause charge to be transferred from the respective interline registers to the first storage register elements based on the interline clocking signals. The second clocking structure part causes charge to be transferred between storage register elements of each storage register based on frame clocking signals.

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Waterloo, Canada

Eric Charles Fox