Intel Corporation

Eric C Samson

Murali Ramadoss

Aditya Navale

Nikos Kaburlasos

Altug Koker

Abhishek R Appu

Balaji Vembu

Joydeep Ray

Subramaniam M Maiyuran

Doron Rajwan

Kun Tian

Ryan Donovan Wells

David J Cowperthwaite

Zhi Hu Wang

Alon Naveh

Efraim Rotem

Paul S Diefenbaugh

Linda L Hurd

Avinash N Ananthakrishnan

David M Puffer

Inder M Sodhi

Josh B Mastronarde

Marc Beuchat

Eliezer Weissmann

Muhammad M Khellah

Barnes Cooper

Stephen H Gunther

Jeremy J Shrall

Eugene Gorbatov

Charles Augustine

Michael N Derr

Andrew D Henroid

Leslie E Cline

Suyoung Bang

Wootaek Lim

Prasoonkumar Surti

Vasanth Ranganathan

Sanjeev S Jahagirdar

Guei-Yuan Lueh

Adam T Lake

Kiran Chand Veernapu

Thomas A Piazza

Zhi Jun Wang

Brian T Lewis

Kalpesh Dhanvantrai Mehta

Phani Kumar Kandula

Siripong Sritanyaratana

Srikrishnan Venkataraman

Robert B Taylor

Ahmed Abou-Alfotouh

Wen-Shan (Vincent) Wang

Mike Donlon

Kenneth Daxer

Elmoustapha Ould-Ahmed-Vall

Varghese George

David Wyatt

David I Poisner

Ravishankar Iyer

Ben J Ashbaugh

Scott R Janus

Guy M Therien

Selvakumar Panneer

Mike MacPherson

Pattabhiraman K

Wenyin Fu

Michael Mishaeli

William A Stevens, Jr

Shai Rotem

Yoni Aizik

Nilesh K Jain

John William Horigan

Barry A O'Mahony

Todd M Witter

Robert T Jackson

Narjala Prakash Bhasker

Zhi Wang

Ariel Berkovits

Robert J Riesenman

Arik Gihon

Jay D Schwartz

Venkatesh Ramani

Ying Cui

Ticky Thakkar

Saurabh Tangri

Win Sheng Cheng

Indraneel Ghosh

Richard W Jensen

Joseph W Tsang

Jayakrishna P S

Sam W Jensen

Chen Ranel

Dinakar Munagala

Madhu Gumma

Julien Fefe Sebot

Jaymin B Jasoliya

Mark A Blake

Pradeep K Golconda

Shalini Sankar

Eliezer Wiessmann

Lakshminarayan Jagannathan

Described herein, in one embodiment, are techniques to facilitate the partial powerdown of sub-components of an execution unit or other graphics processing resource based on the workload to be executed. In another embodiment, granular dynamic voltage and frequency scaling is enabled in which the voltage and frequency of groups of processing resources within a graphics processor can be separately scaled.

Granular GPU DVFS with execution unit partial powerdown

Described herein, in one embodiment, is a graphics processor comprising a plurality of dies integrated in a package, at least one die of the plurality of dies functionally heterogeneous relative to at least one other die of the plurality of dies and manufactured with a different process technology than the at least one other die.

A system includes multiple processors and a power controller. Each processor includes a throttling engine. The power controller is to, in response to a determination that a first power consumption level exceeds a first threshold, assert a critical signal to each throttling engine of the plurality of processors. Further, for each processor, the throttling engine of the processor is to perform a sequence of multiple throttling states while the critical signal is asserted by the power controller, where the sequence of multiple throttling states is performed according to a state machine of the throttling engine. Other embodiments are described and claimed.

System for power throttling

Embodiments described herein include software, firmware, and hardware that provides techniques to enable deterministic scheduling across multiple general-purpose graphics processing units. One embodiment provides a multi-GPU architecture with uniform latency. One embodiment provides techniques to distribute memory output based on memory chip thermals. One embodiment provides techniques to enable thermally aware workload scheduling. One embodiment provides techniques to enable end to end contracts for workload scheduling on multiple GPUs.

Graphics processor operation scheduling for deterministic latency

A distributed and scalable all-digital LDO (D-DLDO) voltage regulator allowing rapid scaling across technology nodes. The distributed DLDO includes many tillable DLDO units regulating a single supply voltage with a shared power distribution network (PDN). The D-DLDO includes an all-digital proportional-integral-derivative (PID) controller that receives a first code indicative of a voltage behavior on a power supply rail. A droop detector is provided to compare the first code with a threshold to determine a droop event, wherein information about the droop event is provided to the PID controller, wherein the PID controller generates a second code according to the first code and the information about the droop event. The DLDO includes a plurality of power gates that receive the second code.

Distributed and scalable all-digital low dropout integrated voltage regulator

Embodiments described herein provide techniques enable a graphics processor to continue processing operations during the reset of a compute unit that has experienced a hardware fault. Threads and associated context state for a faulted compute unit can be migrated to another compute unit of the graphics processor and the faulting compute unit can be reset while processing operations continue.

Compute cluster preemption within a general-purpose graphics processing unit

Methods and apparatus relating to advanced graphics Power State management are described. In one embodiment, measurement logic detects information about idle transitions and active transitions of a power-well of a processor. In turn, determination logic determines performance loss and/or energy gain based at least in part on the detected information and power-on latency of the power-well of the processor. Other embodiments are also disclosed and claimed.

Advanced graphics power state management

Embodiments of systems, apparatuses, and methods for energy efficiency and energy conservation including enabling autonomous hardware-based deep power down of devices are described. In one embodiment, a system includes a device, a static memory, and a power control unit coupled with the device and the static memory. The system further includes a deep power down logic of the power control unit to monitor a status of the device, and to transfer the device to a deep power down state when the device is idle. In the system, the device consumes less power when in the deep power down state than in the idle state.

Method, apparatus, and system for energy efficiency and energy conservation including autonomous hardware-based deep power down in devices

Embodiments described herein provide techniques enable a compute unit to continue processing operations when all dispatched threads are blocked. One embodiment provides for a method comprising executing multiple concurrent threads on a processing resource of a graphics processor, during execution, detecting that each of the multiple concurrent threads of the processing resource are blocked from execution, selecting a victim thread from the multiple concurrent threads, and suspending the victim thread. The thread state is stored to a thread scratch space in memory along with a blocking event associated with the victim thread.

Described is an apparatus comprising a first circuitry and a second circuitry. The first circuitry may process a sequence of Graphics Processing Unit (GPU) commands including an instruction carrying a flag that indicates a workload characteristic corresponding with the sequence of GPU commands. The second circuitry may initiate a power-directed parameter adjustment based upon the flag.

Workload-based maximum current

An apparatus to facilitate data prefetching is disclosed. The apparatus includes a memory, one or more execution units (EUs) to execute a plurality of processing threads and prefetch logic to prefetch pages of data from the memory to assist in the execution of the plurality of processing threads.

Thread prefetch mechanism

An all-digital voltage monitor (ADVM) generates a multi-bit output code that changes in proportion to a voltage being monitored, by leveraging the voltage impact on a gate delay. ADVM utilizes a simple delay chain, which receives a clock-cycle-long pulse every clock cycle, such that the monitored supply voltage is sampled for one full cycle every cycle. The outputs of all delay cells of the delay chain collectively represents a current voltage state as a digital thermometer code. In AVDM, a voltage droop event thus results in a decrease in the output code from a nominal value, while an overshoot results in an increase in the output code.

All-digital voltage monitor (ADVM) with single-cycle latency

Methods and apparatus relating to techniques for power management. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to generate a voltage/frequency curve for at least one of a core or a sub-core in a processor and manage an operating voltage level of the at least one of a core or a sub-core using the voltage/frequency curve. Other embodiments are also disclosed and claimed.

Dynamic voltage-frequency curve mangement

Growing community of inventors

Folsom, CA, United States of America

Eric C Samson