Intel Corporation

Eric C Palmer

Todd B Myers

Jui Min Lim

Nicholas Randolph Watts

Henning Braunisch

Kemal Aygun

Sanka Ganesan

Chandrashekhar Ramaswamy

Renee M Defeo

John Stephen Guzek

Nicolas R Watts

A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein.

Passive within via

Method of embedding passive component within via

A high-speed I/O trace is part of an I/O package architecture for an integrated circuit package substrate. The integrated circuit package substrate includes an integrated heat spreader footprint on a die-side and the I/O trace to couple with an IC device to be disposed inside the IHS footprint. The I/O trace includes a pin-out terminal outside the IHS footprint to couple to an IC device to be disposed outside the IHS footprint. The high-speed I/O trace can sustain a data flow rate from a processor in a range from 5 gigabits per second (Gb/s) to 40 Gb/s.

Input/output package architectures

In some embodiments, package on package using a bump-less build up layer (BBUL) package is presented. In this regard, an apparatus is introduced comprising a microelectronic die having an active surface, an inactive surface parallel to said active surface, and at least one side, an encapsulation material adjacent said at least one microelectronic die side, wherein said encapsulation material includes a bottom surface substantially planar to said microelectronic die active surface and a top surface substantially planar to said microelectronic die inactive surface, a through via connection in said encapsulation material extending from said top surface to said bottom surface, a first dielectric material layer disposed on at least a portion of said microelectronic die active surface and said encapsulation material surface, a plurality of build-up layers disposed on said first dielectric material layer, and a plurality of conductive traces disposed on said first dielectric material layer and said build-up layers and in electrical contact with said microelectronic die active surface. Other embodiments are also disclosed and claimed.

Package on package using a bump-less build up layer (BBUL) package

A method for forming an plurality of paths on a substrate includes drilling an opening for a via to a depth to expose a first pad and a second pad, lining the opening with a conductive material, and insulating a first portion of the lining in the opening from a second portion of the lining in the opening to form a first electrical path contacting the first pad and a second electrical path contacting the second pad.

Via including multiple electrical paths

Input/output package architectures, and methods of using same

A system includes a device having at least one integrated circuit. The integrated circuit further includes a first layer of conductive material, a second layer of conductive material, and a via having multiple electrical paths for interconnecting the first layer of conductive material and the second layer of conductive material. A method for forming a via includes drilling an opening to a depth to expose a first pad and a second pad, lining the opening with a conductive material, and insulating a first portion of the lining in the opening from a second portion of the lining in the opening to form a first electrical path contacting the first pad and a second electrical path contacting the second pad.

Growing community of inventors

Tempe, AZ, United States of America

Eric C Palmer