Inside Technologies

Eric Bouyoux

Bruno Charrat

Jacek A Kowalski

Michel Martin

Sean Commercial

Nicolas Pangaud

The present invention relates to a pipeline microprocessor (MP) comprising a first pipeline stage (ST ) comprising means IPC, MMU, PC, B DEC ) for reading and decoding instructions (CODE , ADRs, ADRd) of a program recorded in a memory (MEM), and a second pipeline stage (ST ), contiguous to the first pipeline stage, comprising two sectors (ST , ST ) activated one after the other during complementary half-cycles of a clock signal (H ) of the microprocessor. The first sector reads data contained in two registers (Rd, Rs) of a bank of registers (BANK , BANK ) of the microprocessor and carries out an operation on the data according to an instruction (CODE , ADRs, ADRd) received at the previous clock cycle. The second sector (ST ) comprises means (B DEC ) to record the result of the operation in a register of the bank of registers (BANK BANK ). Application especially to chip cards.

Two pipeline stage microprocessor and method for processing an instruction

The present invention relates to a pipeline microprocessor (MP , MP ) comprising a program counter (PC), means (MUX, ADD) for the incrementation of the program counter (PC), instruction decoding means (PREDEC, DEC , DEC , DEC ) comprising means (PREDEC) to decode a conditional jump instruction (JMPc) of the program counter, a bank of registers (REGBANK), a computation unit (ALU) comprising a first output (S ) to deliver a result and a second output (S ) to deliver status bits (C, N, P, Z) of the result. According to the invention, the computation unit (ALU) and the means (PREDEC, DEC ) for decoding the conditional jump instruction (JMPc) are laid out in two neighboring pipeline stages (ST , ST ), and the means (PREDEC) for decoding the conditional jump instruction (JMPc) are connected to the second output (S ) of the computation unit (ALU).

Pipeline microprocessor with conditional jump in one clock cycle

A method for selecting an electronic module from a plurality of at least two modules (M M M ) capable of emitting messages simultaneously, includes the steps of sending a general query message (ACTIVALL) to the modules, and selecting (AFI, SELECT-ID) the module having responded first, the modules, on receiving a query message (ACTIVALL, ACTIV), determining a random time interval (P) and sending a responding message (ID, R) when the said time interval (P) has elapsed. A module is set in idle position (IDL) when it receives a message (MESS) before the time interval (P) preceding the sending of a response (ID, R) has elapsed. The idle position (IDL) is at least characterized by the fact that one module does not respond, subsequently, to a complementary query message (ACTIV). This invention is particularly useful for contactless smart card readers and for terminals for electronic labels.

Growing community of inventors

Bouc Bel Air, France

Eric Bouyoux