Micron Technology Incorporated

Eric Blomiley

Durai Vishak Nirmal Ramaswamy

Gurtej S Sandhu

Cem Basceri

Joel A Drewes

Yushi Hu

David H Wells

Fatma Arzum Simsek-Ege

Thomas Gehrke

John Mark Meldrim

Everett Allen McTeer

Ross S Dando

Matthew J King

Jaydip Guha

Jaydeb Goswami

Zailong Bian

Er-Xuan Ping

Allen McTeer

Roger W Lindsay

Danny Dynka

Anurag Jindal

Gowri Damarla

Described are methods for forming multi-component conductive structures for semiconductor devices. The multi-component conductive structures can include a common metal, present in different percentages between the two components of the conductive structures. As described example, multiple components can include multiple ruthenium materials having different percentages of ruthenium. In some applications, at least a portion of one of the ruthenium material components will be sacrificial, and removed in subsequent processing.

Multi-component conductive structures for semiconductor devices

Some embodiments disclose a gate stack having a gate (e.g., polysilicon (poly) material) horizontally between shallow trench isolations (STIs), a tungsten silicide (WSix) material over the gate and the STIs, and a tungsten silicon nitride (WSiN) material on a top surface of the WSix material. Some embodiments disclose a gate stack having a gate between STIs, a first WSix material over the gate and the STIs, a WSiN interlayer material on a top surface of the first WSix material, and a second WSix material on a top surface of the WSiN interlayer material. Additional embodiments are disclosed.

Gate stacks

Some embodiments include a conductive structure which has a first conductive material having a work function of at least 4.5 eV, and a second conductive material over and directly against the first conductive material. The second conductive material has a work function of less than 4.5 eV, and is shaped as an upwardly-opening container. The conductive structure includes a third conductive material within the upwardly-opening container shape of the second conductive material and directly against the second conductive material. The third conductive material is a different composition relative to the second conductive material. Some embodiments include wordlines, and some embodiments include transistors.

Conductive structures, wordlines and transistors

Methods of forming multi-tiered semiconductor devices are described, along with apparatuses that include them. In one such method, a silicide is formed in a tier of silicon, the silicide is removed, and a device is formed at least partially in a void that was occupied by the silicide. One such apparatus includes a tier of silicon with a void between tiers of dielectric material. Residual silicide is on the tier of silicon and/or on the tiers of dielectric material and a device is formed at least partially in the void. Additional embodiments are also described.

Multi-tiered semiconductor apparatuses including residual silicide in semiconductor tier

Some embodiments include formation of at least one cavity in a first semiconductor material, followed by epitaxially growing a second semiconductor material over the first semiconductor material and bridging across the at least one cavity. The cavity may be left open, or material may be provided within the cavity. The material provided within the cavity may be suitable for forming, for example, one or more of electromagnetic radiation interaction components, transistor gates, insulative structures, and coolant structures. Some embodiments include one or more of transistor devices, electromagnetic radiation interaction components, transistor devices, coolant structures, insulative structures and gas reservoirs.

Integrated circuitry

A method of forming a transistor gate construction includes forming a gate stack comprising a sacrificial material received over conductive gate material. The gate stack has lateral sidewalls having insulative material received there-against. The sacrificial material is removed from being received over the conductive gate material to form a void space between the insulative material over the conductive gate material. Elemental tungsten is selectively deposited within the void space over the conductive gate material and a transistor gate construction forming there-from is formed there-from, and which has a conductive gate electrode which includes the conductive gate material and the elemental tungsten. The transistor gate might be used in NAND, DRAM, or other integrated circuitry.

Methods of forming transistor gate constructions, methods of forming NAND transistor gate constructions, and methods forming DRAM transistor gate constructions

This invention includes methods of forming layers comprising epitaxial silicon, and field effect transistors. In one implementation, a method of forming a layer comprising epitaxial silicon comprises epitaxially growing a silicon-comprising layer from an exposed monocrystalline material. The epitaxially grown silicon comprises at least one of carbon, germanium, and oxygen present at a total concentration of no greater than 1 atomic percent. In one implementation, the layer comprises a silicon germanium alloy comprising at least 1 atomic percent germanium, and further comprises at least one of carbon and oxygen at a total concentration of no greater than 1 atomic percent. Other aspects and implementations are contemplated.

The invention includes deposition apparatuses having reflectors with rugged reflective surfaces configured to disperse light reflected therefrom, and/or having dispersers between lamps and a substrate. The invention also includes optical methods for utilization within a deposition apparatus for assessing the alignment of a substrate within the apparatus and/or for assessing the thickness of a layer of material deposited within the apparatus.

Methods for assessing alignments of substrates within deposition apparatuses; and methods for assessing thicknesses of deposited layers within deposition apparatuses

In one implementation, a substrate susceptor for receiving a semiconductor substrate for selective epitaxial silicon-comprising depositing thereon, where the depositing comprises measuring emissivity of the susceptor from at least one susceptor location in a non-contacting manner, includes a body having a front substrate receiving side, a back side, and a peripheral edge. At least one susceptor location from which emissivity is to be measured is received on at least one of the front substrate receiving side, the back side, and the edge. Such at least one susceptor location comprises an outermost surface comprising a material upon which selective epitaxial silicon will not deposit upon during selective epitaxial silicon depositing on a semiconductor substrate received by the susceptor for at least an initial thickness of epitaxial silicon depositing on said substrate. Other aspects and implementations are contemplated.

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Boise, ID, United States of America

Eric Blomiley