Texas Instruments Corporation

Eric Biscondi

Timothy David Anderson

Duc Quang Bui

Mujibur Rahman

Peter Richard Dent

Joseph Raymond Michael Zbiciak

Ashish Rai Shrivastava

Jelena Milanovic

Pierre Bertrand

David J Hoyle

Sundararajan Sriram

Tod David Wolf

Frank Honore

Soujanya Narnur

Shriram D Moharil

Ashish Shrivastava

A Very Long Instruction Word (VLIW) digital signal processor particularly adapted for single instruction multiple data (SIMD) operation on various operand widths and data sizes. A vector compare instruction compares first and second operands and stores compare bits. A companion vector conditional instruction performs conditional operations based upon the state of a corresponding predicate data register bit. A predicate unit performs data processing operations on data in at least one predicate data register including unary operations and binary operations. The predicate unit may also transfer data between a general data register file and the predicate data register file.

Vector SIMD VLIW data path architecture

A processor includes a first and second execution unit each of which is arranged to execute multiply instructions of a first type upon fixed point operands and to execute multiply instructions of a second type upon floating point operands. A register file of the processor stores operands in registers that are each addressable by instructions for performing the first and second types of operations. An instruction decode unit is responsive to the at least one multiply instruction of the first type and the at least one multiply instruction of the second type to at the same time enable a first data path between the first set of registers and the first execution unit and to enable a second data path between a second set of registers and the second execution unit.

Dual register data path architecture with registers in a data file divided into groups and sub-groups

A method for decoding a codeword in a data stream encoded according to a low density parity check (LDPC) code having an m&#xd7;j parity check matrix H by initializing variable nodes with soft values based on symbols in the codeword, wherein a graph representation of H includes m check nodes and j variable nodes, and wherein a check node m provides a row value estimate to a variable node j and a variable node j provides a column value estimate to a check node m if H(m,j) contains a 1, computing row value estimates for each check node, wherein amplitudes of only a subset of column value estimates provided to the check node are computed, computing soft values for each variable node based on the computed row value estimates, determining whether the codeword is decoded based on the soft values, and terminating decoding when the codeword is decoded.

Method and system for decoding low density parity check codes

A digital signal processor (DSP) co-processor according to a clustered architecture with local memories. Each cluster in the architecture includes multiple sub-clusters, each sub-cluster capable of executing one or two instructions that may be specifically directed to a particular DSP operation. The sub-clusters in each cluster communicate with global memory resources by way of a crossbar switch in the cluster. One or more of the sub-clusters has a dedicated local memory that can be accessed in a random access manner, in a vector access manner, or in a streaming or stack manner. The local memory is arranged as a plurality of banks. In response to certain vector access instructions, the input data may be permuted among the banks prior to a write, or permuted after being read from the banks, according to a permutation pattern stored in a register.

Local memories with permutation functionality for digital signal processors

Apparatus and method for optimizing interpolation in the despreader data-path of a wireless telecommunications network employing Code Division Multiple Access (CDMA) technology. A base station dynamically evaluates its configuration to determine an interpolator location. The location of the interpolator in a despreader data-path is dynamically selected. A received signal is interpolated. The despread received signals are combined, and further processing is applied to the combined signal. To enhance system performance, the interpolator may, be located at least to perform chip-sample interpolation per antenna stream at chip rate, chip-sample interpolation per user at chip rate, or symbol-sample interpolation per user at sub-symbol rate.

Dynamic interpolation location

A wireless communication system (). The system comprises a transceiver (), and the transceiver comprises a code counter (LCSTC) and a clock oscillator () for advancing a count in the code counter. The transceiver further comprises circuitry () for receiving a time message based on a system time external from the transceiver and circuitry () for determining a system time count and for storing the system time count to the code counter in response to the time message. Further, code counter continues to be advanced from the system time count in response to the clock oscillator. The transceiver further comprises circuitry () for repeatedly evaluating the count in the code counter, after advancement from the system time count, to ascertain whether the count has drifted to an inaccurate count. Lastly, the transceiver further comprises circuitry (), responsive to detecting an inaccurate count, for adjusting the inaccurate count to a perceived accurate count.

Wireless communication system operating in response in part to time signals from the global position satellite system

A wireless base station (). The base station comprises at least one receive antenna (AT) for receiving communication signals from at least one transmitting station (UST), and the signals are spread with a plurality of chips. The base station further comprises circuitry () for selecting a set of chips corresponding to a first signal received by the at least one receive antenna and circuitry () for forming a set of de-spread chips corresponding to the set of chips and in response to a code. Still further, the base station comprises a functional data path () comprising an accumulator for receiving the set of de-spread chips and circuitry for receiving an instruction. The functional data path is operable in response to a first instruction, received by the circuitry for receiving an instruction, to accumulate (or) a first number of de-spread chips in the set of de-spread chips for producing at least one corresponding symbol. The functional data path is operable in response to a second instruction, received by the circuitry for receiving an instruction, to accumulate () a second number of de-spread chips in the set of de-spread chips for producing an EOL measure.

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Opio, France

Eric Biscondi