Imec Vzw

Imec

Interuniversitair Microelektronica Centrum (imec)

Other

Katholieke Universiteit Leuven

Interuniversitair Micro-electronica Centrum, Vzw

Siemens N.v.

Katholieke Universiteit Leuven, Ku Leuven R&d

Globalfoundries Inc.

Yeda Research and Develpment & Co. Ltd

Universiteit Gent

Vrije Universiteit Brussel

Interuniversitair Micro-elektronica Centrum Vzw

Siemens N.v. and Interuniversitair Micro-electronica Centrum Vzw

Albert-ludwigs-universitat Freiburg

Eric Beyne

Walter De Raedt

Marcel Heerman

Bart Swinnen

Jean Joseph Roggen

Philippe Soussan

Joeri De Vos

Vikas Dubey

Jaber Derakhshandeh

Hendrikus Tilmans

Steven Brebels

Ingrid De Wolf

Deniz Sabuncuoglu Tezcan

Henri Jansen

Joost Wille

Riet Labie

Tom Torfs

Rachel Chechik

Amos Breskin

Maria Op De Beeck

Luc Irena De Schepper

Soon-Wook Kim

Luke G England

Julien Ryckaert

Gustaaf Regina Borghs

Paolo Fiorini

Serge Vanhaelemeersch

Geert Van Der Plas

Maarten Rosmeulen

Jan Vanfleteren

Anabela Veloso

Cedric Huyghebaert

Bogdan Govoreanu

Erik Jan Marinissen

Soeren Steudel

Kaidong Xu

Chris Van Hoof

Patrick Ruther

George Vakanas

Vasile Paraschiv

Sandip Halder

Gerald Beyer

Simon Braun

Jozef Van Puymbroeck

Robert Puers

Stefaan Van Huylenbroeck

Wouter Ruythooren

Bivragh Majeed

Frank Holsteyns

Koen De Munck

Shih-Hung Chen

Herman Oprins

Gerald Peter Beyer

Rita Van Hoof

Yann Civale

Paresh Limaye

Vladimir Cherman

Wenqi Zhang

Ann Dumoulin

Anne Jourdain

Lan Peng

Stefaan Tavernier

Robert Miller

Luc Tielemans

Filip Christiaens

Mikael Detalle

Alexander Mityashin

Khashayar Babaei Gavan

Steven Sanders

Staf Borghs

Raf Vandersmissen

Walter Van Doninck

Giovanni Capuz

Bart Vandevelde

Leonardus Leunissen

Hendrikus A C Tilmans

Steve Lerner

Ronaldo Bellazzini

Hercules Pereira Neves

Nouredine Rassoul

Geraldine Jamieson

Christophe Lorant

Augustin Coello-Vera

Olivier Vendier

Francois Lechleiter

Rita Hoof Van

Jozef Puymbroeck Van

Augustin Coella-Vera

Patrick Verdonck

Myriam Van De Peer

Guy Vandenbosch

Ezzeldin Soliman

Erik Sleeckx

Philip Pieters

Iuliana Radu

Kristel Fobelets

Lin Hou

Jordi Nelissen

Arno Aarts

A method of producing an IC chip is provided. In one aspect, deep trenches are formed in a semiconductor layer that forms the top layer of a device wafer, the trenches going through the complete thickness of the layer. The trenches are filled with a sacrificial material, that is etched back and covered with a capping layer, thereby forming sacrificial buried rails. After processing active devices on the front surface of the semiconductor layer, including connections to the sacrificial rails, the device wafer is bonded face down to a carrier wafer, and thinned from the back side, until the sacrificial rails are exposed. The sacrificial material and the capping layer are removed and replaced by a conductive material, thereby forming the actual buried power rails. A back side power delivery network supplies power through the buried rails to the active devices of the IC. Using a sacrificial material for the buried rails can enable a wider choice of materials for these buried rails.

Method of producing an integrated circuit chip including a back-side power delivery network

A cooling device configured to be mounted in close proximity to an electronic component that is to be cooled is provided. In one aspect, the device includes impingement channels and return channels for guiding a flow of cooling fluid towards and away from a cooled surface of the electronic component. The device also includes a heat exchanger and a pump, so that the flow cycle of a cooling fluid is fully confined within the device itself. The impingement channels, the return channels, and the heat exchanger are integrated in a common housing, which includes an inlet opening and an outlet opening for coupling the device to a refrigerant loop. The pump may be a micropump mounted directly on the housing and coupled to the inlet and outlet openings in the housing. A cooling system including the device and the refrigerant loop is also provided.

Device and system for cooling an electronic component

A method of bonding semiconductor components is described. In one aspect a first component, for example a semiconductor die, is bonded to a second component, for example a semiconductor wafer or another die, by direct metal-metal bonds between metal bumps on one component and corresponding bumps or contact pads on the other component. In addition, a number of solder bumps are provided on one of the components, and corresponding contact areas on the other component, and fast solidified solder connections are established between the solder bumps and the corresponding contact areas, without realizing the metal-metal bonds. The latter metal-metal bonds are established in a heating step performed after the soldering step. This enables a fast bonding process applied to multiple dies bonded on different areas of the wafer and/or stacked one on top of the other, followed by a single heating step for realizing metal-metal bonds between the respective dies and the wafer or between multiple stacked dies. The method allows to improve the throughput of the bonding process, as the heating step takes place only once for a plurality of dies and/or wafers.

Method of direct bonding semiconductor components

A substrate, assembly and method for bonding and electrically interconnecting substrates are provided. According to the method, two substrates are provided, each comprising metal contact structures that are electrically isolated from each other by a bonding layer of dielectric material. Openings are produced in the bonding layer, the openings lying within the surface area of the respective contact structures, exposing the contact material of the structures at the bottom of the openings. Then a layer of conductive material is deposited, filling the openings, after which the material is planarized, removing it from the surface of the bonding layer and leaving a recessed contact patch in the openings. The substrates are then aligned, brought into contact, and bonded by applying an annealing step at a temperature suitable for causing thermal expansion of the contact structures. Deformation of the conductive material of the contact structures through creep pushes the material into the openings from the bottom up, thereby bringing the contact patches into mutual and conductive contact.

Substrate, assembly and method for wafer-to-wafer hybrid bonding

A method is provided for dicing a semiconductor substrate into a plurality of dies, the semiconductor substrate having a front side including a plurality of device areas, a back side, and a plurality of through substrate vias. The method includes defining, from the front side, at least one trench to be formed between adjacent device areas, forming the at least one trench, from the front side of the semiconductor substrate, arranging a protective layer on the front side of the semiconductor substrate, thinning the semiconductor substrate from the back side to reduce the thickness of the semiconductor substrate, processing the back side of the semiconductor substrate to form at least one contact, the contact contacting at least one through substrate via, etching through the minor portion of the thickness of the semiconductor substrate underneath the at least one trench, and dicing the semiconductor substrate into the plurality of dies.

Method for dicing a semiconductor substrate into a plurality of dies

A method for packaging semiconductor dies by overmolding is disclosed. The dies are embedded in a substrate of a mold material, and cavities are produced in the mold substrate by producing 3D structures of a sacrificial material prior to the overmolding step. Afterwards, the sacrificial material is removed to thereby create cavities in the mold substrate. A conformal layer is produced on the 3D structures prior to overmolding, and the mold substrate is thinned to expose an upper surface of the 3D structures. The conformal layer is not removed when the sacrificial structures are removed. In this way, the conformal layer remains on the surfaces of the mold substrate inside the cavity. In one aspect, the conformal layer may have a protective function, useful in the production of packages including dies which come into contact with fluid substances.

Method for packaging semiconductor dies

A method of using sacrificial structures in a mold substrate for packaging a first die and one or more second dies or stacks thereof is disclosed. The method allows testing of the first die prior to mounting the second dies, without requiring a TSV insert. In one aspect, a block of sacrificial material is embedded together with the first die in a first mold substrate and to one side of the first die. The removal of the block creates an opening. The method is configured so that contacts are exposed at the bottom of the opening, the contacts being electrically connected to corresponding contacts on the first die. This may be realized by bonding both the die and the sacrificial block to a redistribution layer, or by mounting a bridge device between the first die and the block prior to a first overmolding applied for producing the first mold substrate. A second die or a stack of second dies is mounted in the opening and bonded to the exposed contacts, after which a second mold substrate is produced, embedding the second die or dies.

A method is disclosed for electrically bonding a first semiconductor component to a second semiconductor component, both components including arrays of contact areas. In one aspect, prior to bonding, layers of an intermetallic compound are formed on the contact areas of the second component. The roughness of the intermetallic layers is such that the intermetallic layers include cavities suitable for insertion of a solder material in the cavities, under the application of a bonding pressure, when the solder is at a temperature below its melting temperature. The components are aligned and bonded, while the solder material is applied between the two. Bonding takes place at a temperature below the melting temperature of the solder. The bond can be established only by the insertion of the solder into the cavities of the intermetallic layers, and without the formation of a second intermetallic layer.

Method for the electrical bonding of semiconductor components

An optical device and a method for fabricating an optical device are described. The optical device may be a light emitting diode (LED) device, e.g. a micro-LED (&#x3bc;LED) device, or a photodiode (PD) device, e.g. an imager. The method comprises processing, on a first semiconductor wafer, an array including a plurality of compound semiconductor LEDs or compound semiconductor PDs and a plurality of first contacts, each first contact being electrically connected to one of the LEDs or PDs. The method further comprises processing, on a second semiconductor wafer, a CMOS IC and a plurality of second contacts electrically connected to the CMOS IC. The method further comprises hybrid bonding the first semiconductor wafer to the second semiconductor wafer such that the plurality of LEDs or PDs are individually connected to the CMOS IC via the first and second contacts.

Method for fabricating an optical device

A method for producing an integrated circuit (IC) chip on a semiconductor device wafer is disclosed. In one aspect, the IC chip includes buried interconnect rails in the front end of line and a power delivery network (PDN) on the back side of the chip. The PDN is connected to the front side by micro-sized through semiconductor via (TSV) connections through the thinned semiconductor wafer. The production of the TSVs is integrated in the process flow for fabricating the interconnect rails, with the TSVs being produced in a self-aligned manner relative to the interconnect rails. After bonding the device wafer to a landing wafer, the semiconductor layer onto which the active devices of the chip have been produced is thinned from the back side, and the TSVs are exposed. The self-aligned manner of producing the TSVs enables scaling down the process towards smaller dimensions without losing accurate positioning of the TSVs.

Method for contacting a buried interconnect rail of an integrated circuit chip from the back side of the IC

The disclosed technology generally relates to integrating semiconductor dies and more particularly to bonding semiconductor substrates. In an aspect, a method of bonding semiconductor substrates includes providing a first substrate and a second substrate. Each of the first substrate and the second substrate comprises a dielectric bonding layer comprising one or more a silicon carbon oxide (SiCO) layer, a silicon carbon nitride (SiCN) layer or a silicon carbide (SiC) layer. The method additionally includes, prior to bonding the first and second substrates, pre-treating each of the dielectric bonding layer of the first substrate and the dielectric bonding layer of the second substrate. Pre-treating includes a first plasma activation process in a plasma comprising an inert gas, a second plasma activation process in a plasma comprising oxygen, and a wet surface treatment including a water rinsing step or an exposure to a water-containing ambient. The method additionally includes bonding the first and the second substrates by contacting the dielectric bonding layer of the first substrate and the dielectric bonding layer of the second substrate to form a substrate assembly. The method further includes post-bond annealing the assembly.

Method of bonding semiconductor substrates

A method for bonding chips to a landing wafer is disclosed. In one aspect, a volume of alignment liquid is dispensed on a wettable surface of the chip so as to become attached to the surface, after which the chip is moved towards the bonding site on the wafer, the bonding site equally being provided with a wettable surface. A liquid bridge is formed between the chip and the bonding site on the substrate wafer, enabling self-alignment of the chip. Dispensing alignment liquid on the chip and not the wafer is advantageous in terms of mitigating unwanted evaporation of the liquid prior to bonding.

Method for bonding semiconductor chips to a landing wafer

An integrated circuit (IC) chip having power and ground rails incorporated in the front end of line (FEOL) is disclosed. In one aspect, these power and ground rails are at the same level as the active devices and are therefore buried deep in the IC, as seen from the front of the chip. The connection from the buried interconnects to the source and drain areas is established by local interconnects. These local interconnects are not part of the back end of line, but they are for the most part embedded in a pre-metal dielectric layer onto which the BEOL is produced. In a further aspect, a power delivery network (PDN) of the IC is located in its entirety on the backside of the chip. The PDN is connected to the buried interconnects through suitable connections, for example metal-filled through-semiconductor vias or through silicon vias.

Integrated circuit chip with power delivery network on the backside of the chip

A liquid cooling system for cooling an electronic device comprising a chip or a chip package comprising a chip is described. The liquid cooling system comprises an inlet plenum comprising a coolant feeding channel oriented substantially parallel with the plane of a main surface to be cooled of the chip and a plurality of inlet cooling channels fluidically connected to the coolant feeding channel and arranged vertically for impinging a liquid coolant directly on said main surface of the chip. The vertically oriented inlet cooling channels are substantially parallel to vertically oriented outlet cooling channels and are separated by a thermally isolating material. The liquid cooling system further comprises at least one cavity wherein a plurality of inlet and outlet cooling channels end. The cavity is arranged for allowing interaction between the liquid coolant and the main surface of the chip and thus comprises a heat transfer region.

Liquid cooling of electronic devices

Provided herein is a method for producing hollow contact areas for insertion bonding, formed on a semiconductor substrate comprising a stack of one or more metallization layers on a surface of the substrate. Openings are etched in a dielectric layer by plasma etching, using a resist layer as a mask. The resist layer and plasma etch parameters are chosen to obtain openings with sloped sidewalls having a pre-defined slope, due to controlled formation of a polymer layer forming on the sidewalls of the resist hole and the hollow contact opening formed during etching. According to a preferred embodiment, metal deposited in the hollow contact areas and on top of the dielectric layer is planarized using chemical mechanical polishing, leading to mutually isolated contact areas. The disclosure is also related to components obtainable by the method and to a semiconductor package comprising such components.

Method for producing contact areas on a semiconductor substrate

Growing community of inventors

Leuven, Belgium

Eric Beyne