International Business Machines Corporation

Arm Limited

Eric Bernard Schorn

Donald George Mikan, Jr

Arthur L Chin

Edmond H Barakat

Marlin Wayne Frederick, Jr

Stephen Larry Runyon

Raymond George Stephany

Howard Lawrence Levy

A voltage controlled oscillator is provided in the form of two ring oscillators,and,Each oscillator stage,includes an invertor,a level change accelerating circuit,and a level change decelerating circuit,The level change accelerating circuit,is responsive to an input control signal Vctrl to increase the oscillator frequency by decreasing the propagation delay through the invertor,The level change decelerating circuit,is responsive to the input control signal Vctrl to decrease the oscillator frequency by increasing the propagation delay through the invertor,Pairs of opposing invertors,and,disposed between output signal lines of corresponding oscillator stages,in the two ring oscillators,and,serve to lock the two ring oscillators in antiphase.

Voltage controlled oscillator with accelerating and decelerating circuits

An edge triggered latch has an improved transparency window, which is essentially the delay of the N-stack pull-down tree. This minimizes the delay yet guarantees that the circuit will have enough time to evaluate the input data, since the evaluation is limited by the pulse width. This circuit eliminates early mode failure for latches placed in series, without the requirement of delay padding.

Edge triggered latch

Switching on a first line, from a first signal level to a second level, tends to induce a change in signal level of a second line. To reduce induced noise, the second line is connected to a power rail for a predetermined time interval, responsive to the switching on the first line. The connecting for the time interval tends to counteract the change induced in the second line by the signal of the first line.

Coupled noise reduction circuitry

Performance is increased within a dynamic multiplexer by removing the foot device and replacing it with a logic gate (such as an OR, NOR, or NAND gate) receiving the select signals and activating the precharge device within the dynamic multiplexer circuit. With such a configuration, crowbar current is still inhibited.

High performance dynamic multiplexers without clocked NFET

One aspect of the invention relates to a method for computer aided optimization of a total cost of an electronic circuit, the total cost being a function of a primary cost and at least one secondary cost, the primary and secondary costs being a function of circuit parameters. In one embodiment, the method comprises the steps of selecting an initial vertice, the vertice being defined by specific values of the circuit parameters; selecting a plurality of additional vertices required to define a region; simulating the circuit to determine the primary costs and the secondary costs associated with the vertices in the region; applying a weighting function to the secondary costs which adjusts the secondary costs relative to the deviation of the secondary costs from a predetermined secondary cost target; aggregating the primary costs and the secondary costs to determine individual total costs associated with the vertices in the region.

Automated method for optimizing characteristics of electronic circuits

One aspect of the invention relates to a method for computer aided optimization of a cost of an electronic circuit, the cost being a function of a plurality of circuit parameters. In one embodiment, the method involves the steps of selecting an initial vertice, the vertice being defined by specific values of the circuit parameters; determining a number of additional vertices required; selecting a plurality of additional vertices which, along with the initial vertice, define a region; simulating the circuit to determine individual costs associated with individual vertices; comparing the individual costs with one another to determine a worst cost; determining a centroid defined by the vertices, excluding the vertice associated with the worst cost; determining a new vertice, the new vertice being located on a line defined by the vertice associated with the worst cost and the centroid, the new vertice being located at a distance away from the centroid, the distance being proportional to a distance factor; simulating the new vertice to determine the associated cost; and comparing a cost associated with the new vertice to a termination criteria.

Automated method for circuit optimization

A logic block comprised of several transistors is provided. The logic block has several inputs and an output for communicating the result of its logic operation. A precharge device having a clock input is connected to the output of the logic block. The precharge device periodically allows the output of the logic block to become valid. This is accomplished by holding the output of the logic block at a fixed voltage level when the clock input is at a first voltage level, and when the clock input changes to a second voltage level, the precharge device allows the result of the logic function performed by the logic block to appear at the output of the logic block. Also, a charge redistribution prevention device is connected to at least one of the transistors included in the logic block. The charge redistribution prevention device prevents charge redistribution by applying a voltage to at least one of the transistors in the logic block. Applying a voltage in this manner equalizes the difference in voltage between internal nodes of the logic block and the output of the logic block, thereby preventing charge from redistributed.

NMOS charge-sharing prevention device for dynamic logic circuits

PMOS charge-sharing prevention device for dynamic logic circuits

A high performance dynamic logic compatible transparent latch is provided. The latch comprises a first switchable invertor circuit, a second invertor circuit, and a third switchable invertor circuit. The first invertor, having a data input, a clock input and an output, is enabled by a first phase of an input clock and is disabled by a second phase of the input clock. The second invertor has an input connected to the first invertor output. The third invertor has a clock input, and is enabled by the second phase of the input clock and disabled by the first phase of the input clock, and further has an input connected to the second invertor output and an output connected to the second invertor input.

High performance dynamic logic compatible and scannable transparent latch

A domino logic circuit includes an evaluation circuit for receiving input signals and performing a logic operation on the input signals, a passgate circuit for controlling the transmission of signals to an output circuit and a feedback latch circuit for holding the output of the evaluation circuit for a predetermined portion of a clock cycle. The output circuit may also include a pair of control transistors to allow the output latching circuit to be turned off during the evaluate portion of the clock cycle thus improving the speed of the domino logic circuit. During the first half of the reset portion of each cycle, the output latching circuit is active and allows the circuit to retain its output state. During the time the passgates are turned off, the evaluate circuit is disconnected and may begin resetting. During the second half of the reset portion of the clocking signal, the passgates open, which allows the output stage to be reset. Since the two additional transistors in the output circuit are controlled by the same signals which control the passgates, the circuit is relatively cheap since only the two transistors must be added to the circuit.

Data processing system and method for improving performance of

A static XOR gate is provided with circuit speeds necessary to meet the increasing demand of higher computer clock frequencies. The XOR of the present invention takes up less area and consumes less power than prior art XOR circuits. Furthermore, time XOR gate of the present invention is fully static and imposes less constraints on the circuit designer, e.g. no reset logic, input synchronization, or the like. The circuit utilizes only NMOS transistors in the functional logic portion with two output inverters. The circuit elements are symmetrical and have identical input loading, output drive and propagation paths. The XOR of the present invention allows multiple gates to be connected in stages as a 'tree' configuration by providing a 'push-pull' XOR/EQV (equivalent, i.e. time complement of the XOR output or XNOR) function which is buffered by output inverters to 'push' the output to a next stage. Additional transistors are provided to help 'pull' internal nodes to the operating voltage but are not logically functional transistors. Further, input connections to the logical transistors are such as to eliminate unnecessary delay between like stages, when configured as a 'tree'.

Fast, low power exclusive or circuit

This invention relates to personal computers, and more particularly to a personal computer system having an Input/Output (I/O) controller which imparts flexibility to the system design and operation. The I/O controller has a plurality of segments. A first segment provides a serial port for exchange of data signals; a second segment provides a parallel port for exchange of data signals; and a third segment provides a selectable interface for connection with a selected one of said option bus and said planar I/O bus. The third segment has a signal line for transmission of a feedback signal indicative of a readiness for transfer of data signals through one of said first and second segments.

Personal computer system with input/output controller having

A system and method is provided which includes a set of N and P type transistors connected such that both positive active and negative dynamic logic input pulses may be received. The pulse catcher circuit of the present invention then outputs a static logic level based upon the input pulses. A first input circuit is included that receives the data signal and outputs a level (voltage or absence of a voltage) to an output invertor circuit which is used in conjunction with a feedback circuit as a latch to maintain the output at the desired level. The feedback circuit ensures that the level will be maintained in a stable state (i.e. ground potential for a logical '0' and Vdd for a logical '1'). In this manner the static logic levels output from the circuit will be maintained until another dynamic pulse is received. Additionally, the pulse catcher circuit will always provide a consistent static logic output, even when both of the dynamic logic input signals are in their active states.

Dynamic to static logic translator or pulse catcher

This invention relates to personal computers, and more particularly to a personal computer system having a signal passing component operatively connected for exchange of data signals with system components operatively connected with a local processor bus and having a segment providing a state machine for receiving external command signals passed on one of the system busses and for passing internal command signals identifying valid data intervals, said state machine requiring a predetermined minimum length of external command signal for issuance of an internal command signal and terminating an internal command signal with termination of an external command signal so as to avoid the adverse effects of crosstalk and transmission line noise on external commands signals and loss of data integrity thereby possibly occurring.

Growing community of inventors

Austin, TX, United States of America

Eric Bernard Schorn