Broadcom Corporation

Apple Inc.

Avago Technologies International Sales Pte. Limited

Avago Technologies General IP (singapore) Pte. Ltd.

Eric Baden

Brian A Childers

John Jeffrey Dull

Mohan V Kalkunte

Michael J Bowes

Puneet Agarwal

Venkateshwar Buduma

Jeff Dull

Ankit Sajjan Kumar Bansal

Sharath Gargeshwari

Ankit Bansal

Curt McDowell

Bruce Hui Kwan

Anupam Anand

Michael A Jorda

Sarath Kumar Immadisetty

Jeff (John) J Dull

Rob Stone

An apparatus and method for timestamping data packets are provided. The apparatus includes an input bit counter responsive to input bits entering a physical layer (PHY) device and an output bit counter responsive to output bits transmitted by the PHY device. A timestamp for an incoming bit is calculated based on a number of bits awaiting transmission by the PHY device at the time of arrival of the incoming bit. The number of bits awaiting transmission by the PHY device is determined based on the first count and the second count.

Apparatus and method for timestamping of data packets

A system or method for logical lane aggregation provides data across a first set of interconnect lanes and determines that at least one interconnect lane is unavailable. The system or method redistributes data to a second set of interconnect lanes, the second set not including the at least one interconnect lane, in response to the at least one interconnect lane being unavailable. The system or method can be used to provide flexible Ethernet logical lane aggregation (FELLA).

Flexible ethernet logical lane aggregation

The present disclosure describes a wired communication device having media access control (MAC) circuitry and physical layer (PHY) circuitry. The MAC circuitry frames one or more data packets in accordance with a wired communication standard or protocol to provide one or more data frames. The one or more data frames include one or more packets that are separated by interpacket gaps (IPGs). The MAC circuitry selectively choses a duration of the IPGs to maintain an average IPG duration. The PHY circuitry encodes the one or more data frames in accordance with a line coding scheme that is efficiently represents different possible combinations for types of characters present in the one or more data frames.

Apparatus and method for wired data communication

A device implementing a forward error correction data transmission system may include at least one processor circuit. The at least one processor circuit may be configured to perform line encoding on a data stream received from a media access control (MAC) module, and periodically insert alignment markers after every number of blocks of the data stream, where the alignment markers are determined based at least in part on a data rate of an associated port. The at least one processor circuit may be further configured to transcode the data stream, where each alignment marker remains contiguous in the transcoded data stream. The at least one processor circuit may be further configured to add parity information to the transcoded data stream. The at least one processor circuit may be further configured to transmit the transcoded data stream over at least one physical lane of the associated port.

Forward error correction (FEC) data transmission system

Methods and apparatus for performing parity and/or ECC operations are disclosed. An example method includes determining that an opcode is being transmitted on a bus and determining if the transmitted opcode is a memory operation. In the event the transmitted opcode is a memory write operation, the example method includes calculating a parity bit for data associated with the opcode, writing the calculated parity bit to a parity table and writing the data to a memory. The example method also includes, in the event the transmitted opcode is the memory read operation, recovering data from a previously written memory, calculating a parity bit for the recovered data, recovering a previously stored parity bit for the recovered data, comparing the parity bit for the recovered data with the previously stored parity bit and, in the event the recovered data parity bit does not match the previously stored parity bit, providing an error notification.

Soft error rate protection for memories

Methods and apparatus for dual hash tables are disclosed. An example method includes logically dividing a hash table data structure into a first hash table and a second hash table, where the first hash table and the second hash table are substantially logically equivalent. The example method further includes receiving a key and a corresponding data value, applying a first hash function to the key to produce a first index to a first bucket in the first hash table, and applying a second hash function to the key to produce a second index to a second bucket in the second hash table. In the example method the key and the data value are inserted in one of the first hash table and the second hash table based on the first index and the second index.

Method and apparatus for dual-hashing tables

A network device for processing packets. The network device includes applying specific fields from a packet to an associated memory device and comparing means for comparing input to the memory device with entries in the memory device. The network device also includes enabling means for enabling selection of bits, by the memory device, that are required to match exactly with bits from the input to the memory device. The network device further includes outputting means for outputting an address for a matched entry by the memory device and applying means for applying a match from the memory device to an associated entry in a table for applying actions from the table that are associated with the match to the packet.

Policy based routing using a fast filter processor

A network device for processing packets. The network device includes an ingress module for performing switching functions on an incoming packet. The network device also includes a memory management unit for storing packets and performing resource checks on each packet and an egress module for performing packet modification and transmitting the packet to an appropriate destination port. Each of the ingress module, memory management unit and egress module includes multiple cycles for processing instructions and each of the ingress module, memory management unit and egress module processes one packet every clock cycle.

Pipeline architecture of a network device

A network device for processing packets. The network devices includes a ingress module for performing lookups for layer 2 switching and performing operations for maintaining a layer 2 table. When the ingress module updates the layer 2 table, the ingress module records the operation performed on the layer 2 table in a modification buffer. Entries are added to the modification buffer when the layer 2 table is modified and in the order in which the layer 2 table was modified. The network device thus enables reconstruction of the layer 2 table by performing the operations in the modification buffer.

System and method for maintaining a layer 2 modification buffer

A system may include a content addressable memory (CAM) that is configured to include multiple services, receive a key, where the key includes source port information and IP information related to a packet received on one of multiple ports, and output a match index value in response to a search of the CAM using the key. The system may include a policy memory module that is configured to receive the match index value and to output meter controls and a meter address based on the match index value, a port meter map module that is configured to receive the source port information and to output a mask value and a per port meter value, and a remapping module that is configured to receive the meter address, receive the mask value and the per port meter value, and modify the meter address based on those values.

Access control list rule compression using meter re-mapping

Various example embodiments are disclosed. According to an example embodiment, a method may include receiving a token count units instruction, periodically increasing or decreasing a token count based at least in part on a refresh rate, and in response to receiving a packet, decreasing or increasing the token count based at least in part on a size of the packet and the instruction.

Token bucket with variable token value

An example network device includes a processor that is configured to apply specific fields from a packet to an associated memory device and comparing means for comparing input to the memory device with entries in the memory device. The example network device is configured to enable selection of bits, by the memory device, that are required to match exactly with bits from the input to the memory device. The specific fields include a plurality of fields some of which include multiple field values and definitions. An input bit map field of one of the plurality of fields is used to provide an additional global mask that is ANDed to associated masks in selected entries in the memory device thereby enabling the memory device to output an OR of the data in the selected entries and thereby allowing multiple ports to share a rule within a memory device entry.

Content aware apparatus and method

A method of handling a datagram in a network device is disclosed. The steps include receiving a datagram, with the datagram having multiple field values, at a port of a network device, parsing the received datagram to obtain the field values, applying the parsed field values to a Ternary Content Addressable Memory (TCAM), determining matches between the parsed field values and predetermined criteria in the TCAM, indexing into a policy table based on the determined matches to obtain an action entry and taking an action based on the obtained action entry.

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Saratoga, CA, United States of America

Eric Baden