Intel Corporation

Eric B Selvin

Andrew M Volk

Krishna Seshan

Yim Pun

Douglas A Guddat

Ali R Farhang

Sajjad A Zaidi

Wing-Cho Fung

A new programmable weak write circuit is defined with the ability to perform SRAM weak write testing at multiple stress strength settings which track process variation. Prior art weak write test circuitry is designed to test a population of SRAM devices at a fixed weak write stress strength as determined by the best available pre-silicon design environmental factors. This design may over- or under-test SRAM cells for the target defects due to poor process tracking characteristics and may require multiple post-silicon design iterations to keep up with environmental changes following initial design. In the new circuit, multiple settings are designed in pre-silicon to account for the expected uncertainty in environmental factors. During post-silicon testing, a suitable stress setting is selected based on an acceptable or predetermined quality versus test yield tradeoff and its suitability is re-evaluated following any significant environmental changes to determine if a different stress setting is necessary.

Programmable weak write test mode

The invention provides in one embodiment thereof an integrated circuit. The integrated circuit includes a first interconnection metallization layer formed upon a substrate. The integrated circuit further includes a second interconnection metallization layer formed upon the first interconnection metallization layer. The second interconnection metallization layer has formed therein at least one signal line coupled to the first interconnection metallization layer. The second interconnection metallization layer has formed therein at least one protective structure that surrounds the signal line.

Structures to mechanically stabilize isolated top-level metal lines

A voltage supply isolation buffer which prevents a voltage applied to an input or output of an IC device from reaching the power supply plane of the device. An inverter circuit is modified such that Vdd is coupled to the source of the p-channel pull-up transistor through a pn diode with the p terminal coupled to Vdd and the n terminal coupled to the source of the p-channel transistor. Under normal operation, Vdd forward biases the diode allowing a high voltage to be applied to the output of the inverter circuit when the p-channel transistor turns on. If, however, a voltage is applied to the output of the inverter circuit by an external voltage supply which is higher than Vdd, the diode will be reverse biased, preventing the voltage at the output node from raising the Vdd level.

Voltage supply isolation buffer

A voltage detector for providing an indication of the power supply level. The voltage detector includes a differential amplifier which compares the core voltage supply with the peripheral voltage supply. An output stage receives the determination and outputs a signal indicating whether the core voltage supply is the same as the peripheral power supply or whether the two are different.

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San Jose, CA, United States of America

Eric B Selvin