Stmicroelectronics S.a.

St-ericsson Sa

Eric Andre

Daniel Saias

Loïc Joet

Fr&eacute;d&eacute;ric Paillardet

Lionel Vogt

Julien Goulier

Sébastien Dedieu

Florent Sibille

Bruno Pellat

Sébastien Lefebvre

Jonathan Amiach

Davy Thevenet

In an embodiment a device includes a first circuit and a second circuit, wherein the first circuit is configured to generate a fourth signal and a fifth signal by applying the phase shift respectively to a first signal and to a second signal and deliver a sixth signal corresponding to a sampling over one bit of the fourth signal, a seventh signal corresponding to a sampling over one bit of the fifth signal, an eighth signal corresponding to a sampling over one bit of a difference between the fourth and fifth signals, and a ninth signal corresponding to a sampling over one bit of a sum between the fourth and fifth signals, wherein the second circuit is configured to receive the sixth, seventh, eighth, and ninth signals and determine, during a first phase where the first and second signals are representative of a first known symbol of a QPSK constellation, a state of a first bit from among a first state and a second state based on the eighth and ninth signals.

Device for compensating a frequency shift

A method and system for measuring a time constant RC of an integrated electronic circuit is provided. This integrated circuit may be made up of a first hardware component and of a second hardware component wherein one of the hardware components is a resistive element and the other is a capacitive element. The first and the second hardware components are connected to an inverting input of an operational amplifier of an integrator of a delta-sigma modulator. A DC voltage is applied to the modulator input. The output signal Qof the modulator is measured with the aid of an analog/digital converter, and the value of the time constant RC is determined on the basis of at least one measurement of the level of the DC component of the output signal Qof the modulator carried out with the air of a measurement counter circuit.

Method and system for measuring a time constant of an integrated circuit, and integrated circuit provided with such a system

A delta-sigma analog-to-digital converter generates a digital signal as a function of an analog signal and a clock signal having a first phase and a second phase. The converter includes a first branch that applies an analog input signal, a feedback branch having a digital-to-analog converter that feeds back an analog reference signal, a loop filter, a quantizer, and a switch. The switch includes, and is timely correlated with, an output switch of the digital-to- analog converter. The switch functions to connect an input resistance on the first branch and disconnect the digital-to-analog converter during the first phase, and disconnects the input resistance and connects the digital-to-analog converter during the second phase.

Delta-sigma analog-to-digital converter and method for operating same

System and method for calibrating a time constant RCi of an integrated electronic current-feedback continuous-time delta sigma analog/digital converter (modulator) having a variable-impedance filter coupled to input of the modulator, an analog input signal Vin of fixed frequency applied to the variable-impedance filter, wherein the analog input signal Vin attenuation engendered by the variable-impedance filter is measured, and the value of a time constant R0Ci in the modulator and value of the impedance of the variable-impedance filter are modified until an attenuation corresponding to the desired attenuation for the integrated electronic circuit modulator is obtained.

System for calibrating a time constant of an integrated circuit, and integrated circuit provided with such a system

A radio signal receiver includes an input for receiving an input signal having an input carrier frequency modulated by a payload signal to be detected. A frequency converter changes the carrier frequency of the input signal and produces an intermediate signal that is an image of the input signal, and has a carrier frequency equal to an intermediate frequency. A filter circuit filters the intermediate signal. A demodulator eliminates a component, with a frequency equal to the intermediate frequency, from the filtered intermediate frequency, and produces the payload signal. The receiver also includes a detection circuit to produce a level signal representative of a level of the payload signal. A control circuit applies a control signal representative of the level signal to a control input of the frequency converter, the filter circuit and the demodulator.

Intermediate-frequency type radio signal receiver

A method for sampling an analogue radiofrequency signal comprising reception of the analogue radiofrequency signal, sending of the received signal on two analogue channels, each channel performing a first signal sampling operation, including a filtering step eliminating signal frequencies that could fold on the useful signal during sampling such that the sampled signal represents a filtered version of the received signal, wherein the sampling frequency is taken to be equal to the frequency of the signal carrier divided by a factor Ndiv1+&#xbd;, Ndiv1 being an integer number, to bring the useful signal to half of the sampling frequency after sampling.

Method of sampling an analogue radiofrequency signal

An analog-digital delta-sigma converter includes a plurality of continuous time integrators for performing a delta-sigma modulation. Each integrator includes at least one charge sharing integrator at a modulator input. One or more pure integrators follow the charge sharing integrator.

Delta-sigma modulator provided with a charge sharing integrator

A method for generating a signal with a frequency equal to a product of a reference frequency and a real number includes providing an output signal from an oscillator, and performing a first integer division of a frequency of the output signal by a first integer divider to obtain a first intermediate signal. A first measurement signal representative of a time difference between the first intermediate signal and a reference signal having the reference frequency is determined. The method further includes generating a first comparison signal derived from the first measurement signal, and generating a second comparison signal dependent on a period of the reference signal, on integer and decimal parts of the real number and on the first integer divider. The first and second comparison signals are compared to obtain an error signal representative of a time difference between a period of a current output signal and the period of the reference signal. The first integer division is deactivated to deliver an error signal to the input of the oscillator, with the output signal from the oscillator forming the desired signal with a frequency equal to the product of the reference frequency and the real number.

Method and device for generating a signal with a frequency equal to the product of a reference frequency and a real number

A &Dgr;&Sgr; modulator including a corrector unit for measuring an error due to differences in the operating parameters of individual components of an internal D/A converter, the corrector unit applying a correction of the error measured in this way to a digital signal, the modulator being characterized in that the internal D/A converter includes a number of individual components greater than the number necessary for internal conversion, and in that the corrector unit is suitable for extracting from the internal conversion process, in alternation, on each occasion a different component from the various individual components in order to measure the operating parameter error of the extracted component, while leaving a number of components in action that is sufficient for internal conversion.

System of DAC correction for a &Dgr;&Sgr; modulator

An analog-to-digital converter including a first module of the type having a series of processor stages, each of the stages performing two conversions of the signal output by the preceding stage, firstly an analog-to-digital conversion and secondly a digital-to-analog conversion, followed by subtracting the signal obtained from the output signal of the preceding stage to provide the analog output signal of the stage. The first module further assembles together the signals digitized by each stage (S , . . . , S ) so as to provide an assembled digital signal (S (nT) which represents the input signal (e(nT) of the converter in digital form. The converter further includes a &Dgr;&Sgr; modulator which digitizes the output signal (b(nT)) from one of the stages, the resulting digitized signal being subtracted from the assembled digital signal (S (nT)

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Hurtieres, France

Eric Andre