International Business Machines Corporation

Eric Adler

Wagdi William Abadeer

William R Tonti

Robert J Gauthier, Jr

Jed Hickory Rankin

Randy William Mann

Jeffrey Scott Brown

Werner A Rausch

Luigi Ternullo, Jr

Subhash Balakrishna Kulkarni

Edward W Sengle

Jonathan M McKenna

Edward J Nowak

Anthony K Stamper

Chung H Lam

Zhong-Xiang He

James Stuart Dunn

James Spiros Nakos

Michael Joseph Zierak

Donald M Kenney

Vidhya Ramachandran

Bradley Alan Orner

Jenifer E Lary

Barbara Ann Waterhouse

Kent E Morrett

John J Ellis-Monaghan

Charles W Koburger, Iii

Terence B Hook

Kerry Bernstein

Dominic Joseph Schepis

Joseph Andrew Iadanza

James Albert Slinkman

Norman Jay Rohrer

Michael John Hargrove

Kenneth John Giewont

Stephen Arthur St Onge

Josef S Watts

Junedong Lee

Judith H McCullen

Henry W Trombley

Neena Garg

Serge Biesemans

Isabel Ying Yang

Micah S Galland

Eric S Phipps

The present invention relates to metal-insulator-metal (MIM) capacitors and field effect transistors (FETs) formed on a semiconductor substrate. The FETs are formed in Front End of Line (FEOL) levels below the MIM capacitors which are formed in upper Back End of Line (BEOL) levels. An insulator layer is selectively formed to encapsulate at least a top plate of the MIM capacitor to protect the MIM capacitor from damage due to process steps such as, for example, reactive ion etching. By selective formation of the insulator layer on the MIM capacitor, openings in the inter-level dielectric layers are provided so that hydrogen and/or deuterium diffusion to the FETs can occur.

Non-continuous encapsulation layer for MIM capacitor

A method for calibrating a software model for a given structure of interest for a variable imposed by an adjacent structure. First determine the spatial extent of the variable imposed by the adjacent structure. Then assign a value to the spatial extent, which varies as a function of distance from the adjacent structure to the given structure. Finally, attach that value to the model of the given structure.

Device modeling for proximity effects

A method for detecting semiconductor process stress-induced defects. The method comprising: providing a polysilicon-bounded test diode, the diode comprising a diffused first region within an upper portion of a second region of a silicon substrate, the second region of an opposite dopant type from the first region, the first region surrounded by a peripheral dielectric isolation, a peripheral polysilicon gate comprising a polysilicon layer over a dielectric layer and the gate overlapping a peripheral portion of the first region; stressing the diode; and monitoring the stressed diode for spikes in gate current during the stress, determining the frequency distribution of the slope of the forward bias voltage versus the first region current at the pre-selected forward bias voltage and monitoring, after stress, the diode for soft breakdown. A DRAM cell may be substituted for the diode. The use of the diode as an antifuse is also disclosed.

Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure

A capacitor structure is fabricated by forming a bottom plate, forming a dielectric layer overlaying the bottom plate, and forming a top plate over the dielectric layer. In addition, at least one insulating sidewall spacer that protects the dielectric layer during processing is formed along the perimeter of the top plate and overlaying a portion of the dielectric layer.

Method of fabricating a capacitor having sidewall spacer protecting the dielectric layer

Non-Continuous encapsulation layer for MIM capacitor

A capacitor structure formed on an insulation layer includes a lower electrode formed on a surface of the insulation layer, a dielectric layer formed on a surface of the lower electrode, an upper electrode formed on a surface of the dielectric layer, a first spacer formed on a side portion of the upper electrode, and a second spacer formed on a side portion of the first spacer and a side portion of the lower electrode. This capacitor structure is formed by depositing a metal-insulator-metal capacitor stack on top of a via, masking and etching an upper electrode of the metal-insulator-metal capacitor stack, depositing and etching a first spacer on an edge surface of the upper electrode, defining a lower electrode of the metal-insulator-metal capacitor based on the first spacer, depositing and etching a second spacer on a surface of the first spacer and an edge of the lower electrode, and forming a wiring layer on a surface of the upper electrode and a surface of the second spacer. This capacitor structure provides a capacitor that is not prone to leakage down the capacitor sidewall and the corresponding method of manufacture provides a capacitor that is fabricated with increased efficiency (e.g., fewer mask steps).

One-mask metal-insulator-metal capacitor and method for forming same

A semiconductor device having a conduction channel which is electrically modulated. A trench structure is formed within a substrate enclosing a diffusion region. The trench structure isolates the devices formed within the diffusion region from the remaining portion of the substrate. The trench walls are made thin enough so that the width of the channel within a diffusion region may be controlled by applying an electrical potential between a trench wall and the substrate. Transistors formed within the trench structure have a conduction channel width controlled by the applied voltage permitting the gain of the transistor to be matched with the gain of other transistors on the substrate.

Semiconductor device and method for making the device having an electrically modulated conduction channel

A varactor circuit having an increased tuning range comprises a first varactor in series with a second varactor between first and second terminals. A resistor is connected between the first and second terminals. A tap of the resistor is connected to a junction of the first and second varactors. This circuit effectively doubles tuning range compared to a single varactor.

Method to increase the tuning voltage range of MOS varactors

A method for detecting semiconductor process stress-induced defects. The method comprising: providing a polysilicon-bounded test diode, the diode comprising a diffused first region within an upper portion of a second region of a silicon substrate, the second region of an opposite dopant type from the first region, the first region surrounded by a peripheral dielectric isolation, a peripheral polysilicon gate comprising a polysilicon layer over a dielectric layer and the gate overlapping a peripheral portion of the first region; stressing the diode; and monitoring the stressed diode for spikes in gate current during the stress, determining the frequency distribution of the slope of the forward bias voltage versus the first region current at the pre-selected forward bias voltage and monitoring, after stress, the diode for soft breakdown. A DRAM cell may,be substituted for the diode. The use of the diode as an antifuse is also disclosed.

A novel method for forming substrate contact regions on a SOI substrate without requiring additional space, and in order to provide lower diffusion capacitance. The method utilizes known semiconductor processing techniques. This method for selectively modifying the BOX region of a SOI substrate involves first providing a silicon substrate. Then, ion implanting the base using SIMOX techniques (e.g. O implant) is accomplished. Next, the substrate is photopatterned to protect the modified BOX region. Then, further ion implanting using a &ldquo;touch-up&rdquo; O implant is accomplished, thereby resulting in a good quality BOX as typically practiced. The final step is annealing the substrate. The area of the substrate, which had a mask present, would not receive the &ldquo;touch-up&rdquo; O implant (second ion implant), which in turn would result in a leaky BOX.

Method of forming a body contact using BOX modification

In an electronic device with an active region on top of and isolated from an substrate, a first material region is defined on top of and/or adjacent to and electrically isolated from the active region and a second material region is attached to a surface of the first material region to form an interface defining a Peltier cooling junction therebetween. A current source connected in series to the first and the second material regions produces a cooling effect at the Peltier cooling junction.

Method and apparatus for cooling a silicon on insulator device

A multigated FET having reduced diffusion capacitance, self-compensating effective channel length, improved short channel effects control, and enhanced density. Forming the FET by providing a plurality of separated insulated gates on a substrate, including forming insulating material on at least four surfaces of each of the gates, forming a dielectric layer on the substrate between the insulated gates, depositing and planarizing a layer of conductive material on and between the insulated gates down to the insulating material on the top surface of the insulated gates, and implanting diffusion regions into the substrate, adjacent to and beneath a portion of two distal ones of the plurality of insulated gates.

Dense multi-gated device design

A capacitor structure includes a bottom plate, a top plate, and a dielectric layer between the bottom and top plates. In addition, at least one insulating sidewall spacer that protects the dielectric layer during processing is formed along the perimeter of the top plate and overlaying a portion of the dielectric layer.

Capacitor having sidewall spacer protecting the dielectric layer

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Jericho, VT, United States of America

Eric Adler