Intel Corporation

Other

Eric A Sprangle

Rajesh Kumar

Herbert H Hum

Anwar Q Rohillah

Doug Carmean

Robert Dale Cavin

Douglas M Carmean

Andrew Thomas Forsyth

Michael Abrash

Tom Forsyth

Edward Thomas Grochowski

Belliappa Manavattira Kuttanna

Ramacharan Sundararaman

John Cruz Mejia

Chris Goodman

Jesus Corbal

Glenn J Hinton

David J Sager

Thomas D Fletcher

Ravi Rajwar

Patrice L Roussel

Ronak Singhal

Joshua B Fryman

Roger Espasa

Michael Haertel

Kenneth J Janik

Lisa K Wu

K S Venkatraman

Toni Juan

Matthew J Craighead

Onur Mutlu

Matt Craighead

Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.

Distribution of tasks among asymmetric processing elements

Techniques to control power and processing among a plurality of asymmetric processing elements are disclosed. In one embodiment, one or more asymmetric processing elements are power managed to migrate processes or threads among a plurality of processing elements according to the performance and power needs of the system.

A technique to share execution resources. In one embodiment, a CPU and a GPU share resources according to workload, power considerations, or available resources by scheduling or transferring instructions and information between the CPU and GPU.

Sharing resources between a CPU and GPU

A device, system and method for assigning values to elements in a first register, where each data field in a first register corresponds to a data element to be written into a second register, and where for each data field in the first register, a first value may indicate that the corresponding data element has not been written into the second register and a second value indicates that the corresponding data element has been written into the second register, reading the values of each of the data fields in the first register, and for each data field in the first register having the first value, gathering the corresponding data element and writing the corresponding data element into the second register, and changing the value of the data field in the first register from the first value to the second value. Other embodiments are described and claimed.

System and method for using a mask register to track progress of gathering and scattering elements between data registers and memory

Systems and methods for migrating processes among asymmetrical processing cores

Techniques to control power and processing among a plurality of asymmetric processing elements are disclosed. In one embodiment, one or more asymmetric processing elements are power managed to migrate processes or threads among a plurality of processing elements according to the performance and power needs of the system

Techniques are disclosed to control power and processing among a plurality of asymmetric cores. In one embodiment, a multi-core processor includes first and second processing cores, each including an arithmetic logic unit and an instruction decoder, wherein the first processing core is capable of operating at a higher processing throughput than the second processing core, wherein the first and second processing cores have different instruction sets, wherein, in response to an occurrence of an event, a task processed on the first processing core is to be translated and transferred to the second processing core after saving a core state of the first processing core and providing the core state to the second processing core, wherein instructions to run on the second processing core are translated to the instruction set of the second processing core by a software binary translation shell, and wherein the first and second processing cores are to concurrently execute instructions according to their own instruction sets.

A processing core is described having execution unit logic circuitry having a first register to store a first vector input operand, a second register to a store a second vector input operand and a third register to store a packed data structure containing scalar input operands a, b, c. The execution unit logic circuitry further include a multiplier to perform the operation (a*(first vector input operand))+(b*(second vector operand))+c.

Super multiply add (super MADD) instructions with three scalar terms

Growing community of inventors

Portland, OR, United States of America

Eric A Sprangle