Nxp B.v.

National Semiconductor Corporation

Eric A M Klumperink

Bram Nauta

Ali Djabbari

Xiang Gao

Ali Kiaei

Gerard G Socci

Mounir Youssef Bohsali

Johannes H A Brekelmans

Zhiyu Ru

A polyphase harmonic rejection mixer, comprising a plurality of stages following each other; wherein a first stage is arranged to perform at least frequency conversion; and a second stage is arranged to perform at least selective weighting and combining; wherein at least two of the plurality of stages are arranged to perform at least combining. In an embodiment, the first stage () comprises three single-ended gain blocks (), arranged to perform selective weighting, frequency conversion and combining; and a second stage () following the first stage () and arranged to perform selective weighting and combining. The second stage () may reduce the number of phases output by the first stage () and may output () a complex differential down converted signal. The mixer may be directly interfaced to an antenna of an LNA-less receiver without weighting in the first stage. The mixer may be included in a software-defined radio.

Polyphase harmonic rejection mixer

Phase-locked loop (PLL) circuitry in which a sampling phase detector samples the output signal in accordance with the reference signal and a frequency detector detects the output signal frequency in accordance with the reference signal.

Phase-locked loop including sampling phase detector and charge pump with pulse width control

Growing community of inventors

Lichtenvoorde, Netherlands

Eric A M Klumperink