Georgia Tech Research Corporation

Erhan Ozalevli

Paul Edward Hasler

David Verl Anderson

Walter Geeshan Huang

Disclosed herein is a reconfigurable mixed signal distributed arithmetic system including: an array of tunable voltage references operable for receiving a delayed digital input signal; a combination device in electrical communication with the array of tunable floating-gate voltage references that selectively combines an output of the array of tunable voltage references into an analog output signal; and a feedback element in electrical communication with the combination device, wherein the array of tunable voltages and the delayed digital input signal combine to perform a distributed arithmetic function and the reconfigurable mixed signal distributed arithmetic system responsively generates the analog output signal.

Reconfigurable mixed-signal VLSI implementation of distributed arithmetic

A digital to analog converter (DAC) includes an operational amplifier and a plurality of ladder elements. Each ladder element includes an epot for providing a voltage, a capacitor, and a switch for selecting between a first voltage and a reference voltage, and for providing the first selected voltage to the first capacitor. The output of the ladder elements are coupled to the inverting input of the operational amplifier. Alternatively, the ladder elements may use tunable floating-gate resistors.

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Atlanta, GA, United States of America

Erhan Ozalevli