Nanonexus Corporation

Advantest (singapore) Pte Ltd

Aptos Corporation

Erh-Kong Chieh

Fu Chiung Chong

Sammy Mok

Frank Swiatowiec

Syamal Kumar Lahiri

Chang-Ming Lin

Joseph Michael Haemer

Roman Milter

David Doan

Yi-Hsing Chen

Tsing-Chow Wang

Te-Sung Wu

William R Bottoms

Nim Cho Lam

Based upon a layout of a semiconductor wafer comprising a plurality of integrated circuits at pre-defined locations, each integrated circuit comprising a set of electrical connection pads, a probe chip contactor is established, having a unit standard cell on the probe side of the probe chip to correspond to each of the arranged integrated circuits. The unit standard cell is stepped and repeated for the probe side of the probe chip contactor, to establish a wafer scale standard cell layout. The opposite contact side of the probe chip contactor is connectable to a central structure, e.g. a Z-block or PC board, typically comprising a fixed array of vias with fixed X, Y, and Z locations. The routing of contact side of the probe chip contactor is preferably routed automatically, such as implemented on one or more computers, to provide electrical connections between the substrate through vias and the Z-block through vias.

Structures and processes for fabrication of probe card assemblies with multi-layer interconnect

This invention provides a solution to increase the yield strength and fatigue strength of miniaturized springs, which can be fabricated in arrays with ultra-small pitches. It also discloses a solution to minimize adhesion of the contact pad materials to the spring tips upon repeated contacts without affecting the reliability of the miniaturized springs. In addition, the invention also presents a method to fabricate the springs that allow passage of relatively higher current without significantly degrading their lifetime.

Miniaturized contact spring

Within a method for fabricating a microelectronic fabrication there is first provided a substrate. There is then formed over the substrate a patterned bond pad layer. There is also formed over the substrate and in electrical communication with the patterned bond pad layer a patterned redistribution layer, wherein the patterned redistribution layer is formed employing a plating method. The method is particularly economical for fabricating the microelectronic fabrication.

Method for fabricating a microelectronic fabrication having formed therein a redistribution structure

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Cupertino, CA, United States of America

Erh-Kong Chieh