Industrial Technology Research Institute

Erh-Chiao Wang

Wei-Kuo Chia

Chun-Yang Cheng

An address generator is disclosed for performing 2-D virtual coordinate to linear physical memory address conversion. The address generator has an edge walking circuit which receives a 2-D virtual coordinate of a first pixel on a first edge of an object displayed on the display screen. The edge walking circuit selectively outputs a 2-D virtual coordinate of a second pixel which intercepts the first edge of the object at an adjacent pixel row or column to the first pixel. The address generator also has a span expansion circuit which receives the 2-D virtual coordinate of the second pixel. The span expansion circuit selectively expands the 2-D virtual coordinate of the second pixel, according to the number of bits used to represent each pixel and the amount of information which can be accessed at a time from memory. This produces first and second expanded coordinates of the second pixel. Furthermore, the address generator has a linear address circuit which receives the first and second expanded coordinates of the second pixel. The linear address circuit outputs a linear physical address of the second pixel in memory.

Growing community of inventors

Taoyuan, Taiwan

Erh-Chiao Wang