Freescale Semiconductor,inc.

Eyesight Mobile Technologies Ltd.

Erez Steinberg

Yehuda Yitschak

Yong Yan

Moshe Anschel

Itay S Peled

Rotem Porat

Itay Katz

Uri Dayan

Ziv Zamsky

Idan Rozenberg

Shai Koren

Aviram Amir

Itzhaki Barak

Ron Shaposhnikov

Srirama Rao Garikipati

Rajeev Tiwari

Shahar Nahum

Roey Lehmann

Moshe Nakash

Yaniv Klein

Yehuda Yitshcak

Systems, devices, methods, and non-transitory computer-readable media are provided for gesture recognition and control. For example, a processor of a gesture recognition system may be configured to receive first image(s) from an image sensor and process the image(s) to detect a first position of an object. The processor may also define a first navigation region in relation to the position and define a second navigation region in relation to the first navigation region, the second region surrounding the first region. The processor may also receive second image(s) from the image sensor and process the image(s) to detect a transition of the object from the first region to the second region. The processor may also determine a first command associated with a device and that corresponds to the transition of the object from the first region to the second region and provide the determined command to the device.

Gesture recognition control device

Video processing system, computer program product and method for managing an exchange of information between a memory unit and a decoder, the method includes: (a) retrieving, from the memory unit, a first non-zero data structure that comprises only non-zero first transform coefficient groups; wherein first transform coefficient groups are associated with a first quality level; (b) retrieving, from the memory unit, second layer information; (c) processing, by the video decoder, the second layer information and the first non-zero data structure to provide second transform coefficient groups; (c) generating, by the video decoder, a second non-zero data structure that comprises only non-zero second transform coefficient groups; wherein the second non-zero data structure is associated with a second quality level that is higher than the first quality level; (d) generating second non-zero indicators that are indicative of non-zero transform coefficient groups, wherein the second non-zero data structure is associated with a second quality level that is higher than the first quality level; and (e) writing to the memory unit the second non-zero indicators.

Video processing system, computer program product and method for managing a transfer of information between a memory unit and a decoder

A method of encoding a video frame is disclosed in which video slices of the video frame are initially encoded in parallel using both interframe encoding and intraframe encoding. Then, after a first predetermined minimum amount of the video frame has been encoded, the method includes periodically determining whether the amount of intraframe encoded information for the frame achieves a first threshold, and when the first threshold is achieved, encoding the remainder of the video frame using only intraframe encoding. The method may include determining whether a lower second threshold is achieved based on relative complexity of the frame and quantization. The method may include performing similar comparisons on a slice by slice basis in which any one or more of the processing devices skips motion estimation and interframe encoding for corresponding video slices. A video encoder is disclosed which includes multiple processing devices and a shared memory.

Video scene change detection and encoding complexity reduction in a video encoder system having multiple processing devices

Embodiments are disclosed for a system and method for parallel processing of video signals. A multi-core processor is used to establish a master-slave relationship between a first processing core and a plurality of individual processing cores. Shared memory is used to store data and control messages. A plurality of individual private memories are associated with each of the individual processing cores; and control logic is used to establish a master-slave protocol for using the plurality of individual cores to process video data. The master processing core is operable to balance the video data processing load among the individual slave processing cores.

System and method for parallel video processing in multicore devices

A method for generating cache user initiated pre-fetch requests, the method comprises initiating a sequence of user initiated pre-fetch requests; the method being characterized by: determining the timing of user initiated pre-fetch requests of the sequence of user initiated pre-fetch requests in response to: the timing of an occurrence of a last triggering event, a user initiated pre-fetch sequence delay period and a user initiated pre-fetch sequence rate.

Device and method for generating cache user initiated pre-fetch requests

A method for executing an instruction, the method includes: executing a compare and configure mask instruction, wherein the executing comprises: performing a comparison to provide a comparison result; and configuring, in response to the comparison result, a multiple bit mask that is stored in a multiple-purpose register; wherein all bits of the multiple bit mask are configured to have the same value; and applying an algorithmic operation on the multiple bit mask to provide an algorithmic operation result; wherein the algorithmic operation result represents an outcome of a high level programming language conditional statement.

System, method and computer program product for executing a high level programming language conditional statement

A method for address comparison, the method includes: (i) receiving an input address; (ii) determining whether the input address is within a memory segment out of a group of memory segments by comparing, in parallel, the input address to memory segment boundaries of each memory segment of the group; (iii) wherein a comparison between the input address and a memory segment boundary comprises: (a) applying a XOR operation on bits of a most significant portion of the input address and corresponding bits of a most significant portion of the memory segment boundary; (b) ignoring bits of a least significant portion of the input address and corresponding bits of a least significant portion of the memory segment boundary; and (c) comparing, by utilizing a set of full comparators, between bits of an intermediate portion of the input address and corresponding bits of an intermediate portion of the memory segment boundary; wherein a location of bits that form the intermediate portion of the input address and of the memory segment boundary is selected in response to an alignment restriction imposed on the memory segment, to a size of the memory segment and in response to a boundary restriction imposed on the memory segment.

Method for address comparison and a device having address comparison capabilities

Growing community of inventors

Tel Aviv, Israel

Erez Steinberg