Intel Corporation

Erez Carmel

Thomas F Heil

Stephen Anthony Fischer

Robert N Murdoch

Craig S Walker

Jayawant V Oak

A memory controller apparatus for controlling access to a memory array from a microprocessor and a plurality of devices is described. The memory controller apparatus interfaces the microprocessor and the plurality of devices. The microprocessor functions asynchronously with the plurality of devices. The memory controller apparatus comprises a delay line circuitry coupled to receive a selected request for accessing the memory array from one of the microprocessor and the plurality of devices, the delay line means further including means for generating a plurality of memory timing control signals. The memory timing control signals are used for accessing the memory array. The delay line circuitry functions independently of any clock signal. The delay line circuitry is only triggered by the selected request. The memory controller apparatus further comprises a memory state circuitry coupled to the delay line circuitry for controlling sequence and timing of the memory timing control signals. The memory state circuitry is clocked by the memory timing control signals. A method of generating memory timing control signals in a memory controller apparatus is also described.

Memory controller with integrated delay line circuitry

A means and a method of interfacing a memory controller with a high speed synchronous CPU wherein the CPU clock is independent of the memory controller clock. The CPU clock is connected to both the CPU and a control interface state tracker located externally to the memory controller. The control interface state tracker is then connected to the memory controller. A separate clock independent from the one used with the CPU is coupled to the memory controller and drives the operation of the memory controller. During the operation of the computer system, the CPU makes read or write cycle requests of the memory controller. Such cycles are initiated when the CPU sends a cycle 'start' indicator to the state tracker. In response, the state tracker activates a start strobe to the memory controller to start the actual memory cycle. The memory controller receives the CPU address and cycle status and determines the page hit/miss condition of the memory access. Using this information, the appropriate register in the cycle length register file is accessed to obtain a cycle length feedback value indicating the quantity of wait states necessary for the particular memory cycle. This cycle length feedback value is sent to the external control interface state tracker. The state tracker then returns a ready indication to the CPU after the cycle length time has been satisfied as indicated by the cycle length feedback.

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Sacramento, CA, United States of America

Erez Carmel