Marvell Israel (misl) Ltd.

Marvellworld Trade Ltd.

Other

Arm Limited

Erez Amit

Erez Izenberg

Dimitry Melts

Eitan Joshua

Oren Shafrir

Shaul Chapman

Sujat Jamil

Frank O'Bleness

Moshe Raz

Amit Shmilovich

Oren Ben-Hayune

Arie Elias

R Frank O'Bleness

Noam Mizrahi

Ruven Torok

Husam Khshaiboun

A cluster of processing elements has a split mode in which the processing elements are configured to process independent processing workloads, and a lock mode in which the processing elements comprise at least one primary processing element and at least one redundant processing element, each redundant processing element configured to perform a redundant processing workload for checking an outcome of a primary processing workload performed by a corresponding primary processing element. A shared cache is provided, having a predetermined cache capacity accessible to each of the processing elements when in the split mode. In the lock mode, the predetermined cache capacity of the shared cache is fully accessible to the at least one primary processing element.

Cluster of processing elements having split mode and lock mode

In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network.

Interconnected ring network in a multi-processor system

Methods and systems for implementing versatile optical terminals that detect optical transmission protocols and subsequently adapt to the correct protocol are disclosed. In an embodiment, an interface device for providing an interface for a first network with a passive optical network (PON) is disclosed. The interface device includes a protocol detection circuit for determining whether optical communication signals received from the PON conform to a first optical communication protocol, and a switchover control circuit that reconfigures the interface device to work with a second optical communication protocol when the received optical communication signals do not conform to the first optical communication protocol.

Versatile optical network interface methods and systems

A data unit is received, wherein the data unit includes a primary information data structure and a primary redundancy data structure. A secondary error correction operation is performed on one or more selected fields within the primary information data structure. After performing the secondary error correction operation, a primary error correction operation is performed on the data unit using the primary redundancy data structure, the primary error correction operation separate from the secondary error correction operation.

Method and apparatus for enhanced error correction

A data unit is received, wherein the data unit includes a primary information data structure and a primary redundancy data structure. A field in the primary information data structure is detected. A secondary error correction operation is performed on the detected field. After performing the secondary error correction operation, a primary error correction operation is performed on the data unit using the primary redundancy data structure.

Some of the embodiments of the present disclosure provide a method for scheduling processing of packets received from a network, comprising assigning a corresponding queue weight to each of a plurality of queues that are configured to enqueue the packets for processing; for each of the plurality of queues, determining a corresponding multiplication factor (MF) as a function of a number of cycles until a next packet is available from the corresponding queue for processing; and incrementing a plurality of counters, associated with the corresponding plurality of queues, based at least in part on the multiplication factors. Other embodiments are also described and claimed.

Deficit round robin scheduling using multiplication factors

In accordance with the teachings described herein, systems and methods are provided for performing forward error correction. A decoder for performing forward error correction for a frame in a data stream includes a state machine configured to determine if a code block within the frame received by the decoder is a complete code block or a partial code block, the frame including a plurality of code blocks. A decoding unit is configured to receive the code block, and, when the code block is a partial code block, to generate an output based on decoding the partial code block and an additional partial decoding result that is input to the decoding unit.

Systems and methods for performing forward error correction

Some of the embodiments of the present disclosure provide a method for operating a first in first out (FIFO) memory system in different clock domains, the method comprising receiving a write request in a first clock domain; generating, by a write shift and truncation module in response to receiving the write request, a shifted series of binary numbers such that the shifted series of binary numbers is a reduced sub-set of a first series of binary numbers; and generating, by a binary to Gray conversion module, a series of Gray code numbers corresponding to the shifted series of binary numbers. Other embodiments are also described and claimed.

Growing community of inventors

Chandler, AZ, United States of America

Erez Amit