Intel Corporation

Erdinc Ozturk

Vinodh Gopal

Gilbert M Wolrich

Wajdi K Feghali

James D Guilford

Martin Guy Dixon

Kirk S Yap

Sean M Gulley

Sean Mirkes

Bret L Toll

Mark C Davis

Alexandre J Farcy

Maxim Loktyukhin

Kahraman D Akdemir

Deniz Karakoyunlu

Matthew C Merten

Tong Li

Shay Gueron

Daniel Cutter

Robert S Chappell

Pierre Laurent

Gunnar Gaubatz

Robert P Ottavi

John J Vranich

Andrew Milne

Matt Bace

Bret T Toll, I

Schuyler Eldridge

Jim D Guilford

James D Gulilford

Waidi K Feghali

Vindoh Gopal

Maxim Loktyukin

Kaan Yuksel

A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag.

Rotate instructions that complete execution either without writing or reading flags

A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.

Method and apparatus to process SHA-2 secure hashing algorithm

A number of addition instructions are provided that have no data dependency between each other. A first addition instruction stores its carry output in a first flag of a flags register without modifying a second flag in the flags register. A second addition instruction stores its carry output in the second flag of the flags register without modifying the first flag in the flags register.

Addition instructions with independent carry chains

A processor includes a plurality of registers, an instruction decoder to receive an instruction to process a KECCAK state cube of data representing a KECCAK state of a KECCAK hash algorithm, to partition the KECCAK state cube into a plurality of subcubes, and to store the subcubes in the plurality of registers, respectively, and an execution unit coupled to the instruction decoder to perform the KECCAK hash algorithm on the plurality of subcubes respectively stored in the plurality of registers in a vector manner.

Method and apparatus to process KECCAK secure hashing algorithm

Method and apparatus for performing a shift and XOR operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources perform a shift and XOR on at least one value.

Method and apparatus for performing a shift and exclusive or operation in a single instruction

A method in one aspect may include receiving a multiply instruction. The multiply instruction may indicate a first source operand and a second source operand. A product of the first and second source operands may be stored in one or more destination operands indicated by the multiply instruction. Execution of the multiply instruction may complete without writing a carry flag. Other methods are also disclosed, as are apparatus, systems, and instructions on machine-readable medium.

Multiplication instruction for which execution completes without writing a carry flag

An embodiment may include circuitry that may be capable of performing compression-related operations that may include: (a) indicating, at least in part, in a data structure at least one position of at least one subset of characters that are to be encoded as a symbol, (b) comparing, at least in part, at least one pair of multi-byte data words that are of identical predetermined fixed size, (c) maintaining, at least in part, an array of pointers to potentially matching strings that are to be compared with at least one currently examined string, and/or (d) allocating, at least in part, a first buffer portion to store at least one portion of uncompressed data from an application buffer that is to be input for compression to produce a compressed data stream.

Techniques to accelerate lossless compression

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Marlborough, MA, United States of America

Erdinc Ozturk