Synopsys, Inc.

Erdem Cilingir

Srini Arikati

Weiping Fang

Soo Han Choi

Marco Hug

Srinivasa R Arikati

A method is presented for layout decomposition including creating a first graph representative of an integrated circuit layout to be multiple-patterned, when a computer is invoked to decompose the layout, and decomposing each of a first subset of a multitude of sub-graphs into at least three sets when a valid coloring solution is returned for the layout. The multitude of sub-graphs is created from the first graph by dividing the first graph. The method further includes approximately decomposing each of the first subset into at least three sets using a hybrid evolutionary algorithm when the hybrid evolutionary algorithm does not return a valid coloring solution for the layout, and forming a colored graph representative of the layout by merging the at least three sets to generate one of at least three colors for each one of a multitude of vertices of the first graph.

Hybrid evolutionary algorithm for triple-patterning

A computer implemented method for validating a design is presented. The method includes generating, using the computer, a graph non-decomposable to a colored graph representative of the design, when the computer is invoked to validate the design. The method further includes identifying, using the computer, at least one guidance to at least one conflict in a mask layout associated with the design, the conflict causing the graph to be non-decomposable.

Detecting and displaying multi-patterning fix guidance

According to one embodiment of the present invention, a computer-implemented method for validating a design includes generating, using the computer, a first graph representative of the design, when the computer is invoked to validate the design, and decompose, using the computer, the first graph into at least three sets using a hybrid evolutionary algorithm to form a colored graph.

A method for making a multitude of masks for manufacturing an integrated circuit includes receiving the integrated circuit design printable using a multiple-patterning process. The design includes shapes and at least one layout conflict preventing decomposition of the design into the multitude of masks. The method further includes forming a subset of the shapes including the shapes associated with the at least one layout conflict. The method further includes categorizing the shapes of the subset into one of a multitude of topology types, generating stitch candidate solutions for the multitude of topology types, and decomposing the design into a multitude of masks. The subset of the multitude of shapes is formed by generating a first graph representative of the design, decomposing the first graph into at least three colors to form a colored graph; and identifying within the first graph, a second graph including at least one conflict edge.

Categorized stitching guidance for triple-patterning technology

A computer-implemented method for validating a design is disclosed. The method includes receiving, with the computer, the design, where the design is printable using a multiple-patterning process when the computer is invoked, and where the design includes a plurality of shapes and at least one conflict preventing decomposition of the design into a plurality of multiple-patterning masks. The method also includes forming a subset of the shapes, the subset including the shapes associated with the at least one conflict, categorizing each of the shapes of the subset into one of a plurality of topology types generating one or more stitch candidate solutions for each of the plurality of topology types, and decomposing the design into a plurality of masks.

Growing community of inventors

Sunnyvale, CA, United States of America

Erdem Cilingir