Apple Inc.

Eran Tamari

Lior Zimet

Per Hakan Hammarlund

Sergio Kolor

Jonathan M Redshaw

Steven John Fishwick

Harshavardhan Kaushikkar

Gaurav Garg

James Vash

Sagi Lahav

Steven R Hutsell

Shawn Munetoshi Fukami

Sergio V Tota

Jeffry E Gonion

Gerard Richard Williams

Tzach Zemer

Yafei Bi

Arthur L Spence

Vanessa Cristina Heppolette

Opher D Kahn

Josh P DeCesare

Alfredo Kostianovsky

Haim Hauzi

Idan Nissel

Leonid Gitelman

Oren Betzalel

Dalia R Haim

In an embodiment, a system includes a plurality of integrated circuits have subsets of a plurality of agents. The plurality of integrated circuits may have network segments implemented wholly (e.g., entirely) within the respective integrated circuits and may have segment to segment (S2S) network interface circuits to couple to other network segments of a plurality of network segment forming a network among the plurality of agents.

Segment to segment network interface

A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture.

Scalable system on a chip

A chip design methodology and a set of integrated circuits that are taped out from a common design database are disclosed. The area of a full instance of the integrated circuit is defined, and one or more chop lines are defined to identify portions that will be removed for one or more partial instances. A variety of techniques and mechanisms are defined to permit the tape outs to occur from a common design database, so that the effort to tape out partial instances may be minimized beyond that to tape out the full instance.

Full die and partial die tape outs from common design

In an embodiment, a system may support programmable hashing of address bits at a plurality of levels of granularity to map memory addresses to memory controllers and ultimately at least to memory devices. The hashing may be programmed to distribute pages of memory across the memory controllers, and consecutive blocks of the page may be mapped to physically distant memory controllers. In an embodiment, address bits may be dropped from each level of granularity, forming a compacted pipe address to save power within the memory controller. In an embodiment, a memory folding scheme may be employed to reduce the number of active memory devices and/or memory controllers in the system when the full complement of memory is not needed.

Hashing with soft memory folding

In an embodiment, a system on a chip (SOC) comprises a semiconductor die on which circuitry is formed, wherein the circuitry comprises a plurality of agents and a plurality of network switches coupled to the plurality of agents. The plurality of network switches are interconnected to form a plurality of physical and logically independent networks. A first network of the plurality of physically and logically independent networks is constructed according to a first topology and a second network of the plurality of physically and logically independent networks is constructed according to a second topology that is different from the first topology. For example, the first topology may a ring topology and the second topology may be a mesh topology. In an embodiment, coherency may be enforced on the first network and the second network may be a relaxed order network.

Multiple independent on-chip interconnect

Systems and methods for synchronizing a video source and display circuitry using a dynamic tearing effect (TE) signal are provided. In one embodiment, an electronic display device includes: variable refresh rate circuitry that, when no new frame data is provided to the electronic display device, extends a vertical blanking period and reduces a refresh rate of the electronic display device. A tearing effect signal is generated, which is selectively set to a first logical level at a first period of time and a second logical level at a second period of time. The tearing effect signal is provided to the host electronic device that provides frame data to the electronic display device and upon receipt of new frame data, an un-extended vertical blanking period is returned to and the frame data at the next frame boundary is displayed.

Variable refresh rate display synchronization

Growing community of inventors

Herzeliya Pituach, Israel

Eran Tamari