Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Ramot at Tel-aviv University Ltd.

Sandisk Il Ltd.

Infineon Technologies Ag

Sandisk Corporation

Romat at Tel Aviv University Ltd.

Sandisk Ii, Ltd.

Eran Sharon

Idan Alrod

Alexander Bazarsky

Ariel Navon

Simon Litsyn

Ran Zamir

Omer Fainzilber

Stella Achtenberg

Menahem Lasser

Dudy David Avraham

Evgeny Mekhanik

Yan Li

Shay Benisty

David Avraham

Idan Goldenberg

Mark Murin

Ishai Ilani

Alon Eyal

Alex Bazarsky

Yehuda Hahn

Alon Marcu

Nima Mokhlesi

Dana Lee

Tz-Yi Liu

David Rozman

Tianhong Yan

Karin Inbar

Mark Shlick

Tomer Tzvi Eliash

Rami Rom

Noam Presman

Nika Yanuka

Liang Pang

Hadas Oshinsky

Tien-Chien Kuo

Yan Dumchin

Yuri Ryabinin

Ofer Shapira

Nian Niles Yang

Gerrit Jan Hemink

Raul-Adrian Cernea

Kevin M Conley

Toru Miwa

Rajeev Nagabhirava

Damian Pablo Yurzola

Joanna Lai

Sergey Anatolievich Gorobets

Seungjune Jeon

Amir Shaharabany

Grishma Shah

Jack Frayer

Julian Vlaiko

Tomer Eliash

Xinmiao Zhang

Opher Lieber

Yee Lih Koh

Arthur Shulkin

Nimrod Hermesh

Deepanshu Dutta

Christopher John Petti

Richard Leo Galbraith

Jianmin Huang

Itzhak Pomerantz

Yu-Chung Lien

David Robison Hall

Chris Avila

Amit Kumar Sharma

Gautam Ashok Dusija

Yoav Weinberg

Daniel Joseph Linnen

Xinde Hu

Changyuan Chen

Kirubakaran Periyannan

Rohit Sehgal

Jonas Andrew Goode

Gadi Vishne

Gopinath Balakrishnan

Mai Ghaly

Refael Ben-Rubi

Marina Frid

Arseniy Aharonov

Igor Genshaft

Abhinandan Venugopal

Shahar Bar-Or

Rahav Yairi

Vinayak Bhat

Ofir Pele

Michael Micha Ionin

Asaf Gueta

Yossi Erlich

Yair Baram

Uri Peltz

Gen Pei

Wanfang Tsai

Henry Yip

Itshak Afriat

Michal Silbermintz

A Harihara Sravan

Yigal Eli

Lanlan Gu

A shared decoder pool is susceptible to head-of-line blocking when the decoding of a given data block delays the decoding of other data blocks pipelined in the decoder. While the problem can be avoided by not using a pipeline operation, the benefits of pipelining would be lost. In one embodiment provided herein, the syndrome of an error pattern is calculated in parallel with data being written in an input buffer for the decoder. Parallelizing the syndrome calculation and the filling of the decoder's input buffer can avoid the head-of-line blocking problem noted above while still achieving the benefits of pipelining. In another embodiment, a similar technique is used in a bit error rate estimation scan (BES) operation. Other embodiments are provided.

Data storage device with efficient decoder pool and method for on-the-fly decoder initialization

For bit errors caused by intrinsic cell variations, the bit errors are scattered across a page of memory. However, for bit errors caused by a physical issue in memory, the bit errors cluster together within the same memory area. In an example data storage device, a page of memory is divided into sections, and counters are used to count the number of errors in each section. A physical error location is detected if the number exceeds a parameter, and as compared to the number of errors in the other sections. In another example data storage device having an error correction code (ECC) engine, a histogram and binomial probability are used to detect physical errors. This has the advantage of detecting weak memory blocks that are about to fail, so the blocks can be retired early as a grown bad block.

Data storage device and method for identifying a failing area of memory based on a cluster of bit errors

A storage system has an inference engine that can infer a read threshold based on a plurality of parameters of the memory. The read threshold can be used in reading a wordline in the memory during a regular read operation or as part of an error handling process. Using this machine-learning-based approach to infer a read threshold can provide significant improvement in read threshold accuracy, which can reduce bit error rate and improve latency, throughput, power consumption, and quality of service. In another embodiment, a storage system is configured to use a binary full-depth symmetrically-sorted tree to infer a read threshold based on a plurality of parameters of the memory.

Storage system and method for implementation of symmetric tree models for read threshold calibration

Methods and apparatus for power management in data storage devices are provided. One such data storage device (DSD) includes a non-volatile memory (NVM), a set of hardware processing engines, and a power sensor to detect a total power consumption of the set of hardware processing engines. A processor is configured to determine a power-per-processing event value for each of the set of processing engines based on total power consumption measurements, then control delivery of power to the processing engines based on the power-per-processing event values in accordance with a power budget. In some examples, the DSD employs a least-squares procedure to estimate the power-per-processing event values so the values can be determined without needing to measure the individual power consumption of the processing engines. Exemplary processing engines include a Read engine, a Write engine, etc. A recursive least-squares update procedure is also described.

Power-per-processing event estimates based on total power consumption measurements within a data storage device

A storage system has an inference engine that can infer a read threshold based on a plurality of parameters of the memory. The read threshold can be used in reading a wordline in the memory during a regular read operation or as part of an error handling process. Using this machine-learning-based approach to infer a read threshold can provide significant improvement in read threshold accuracy, which can reduce bit error rate and improve latency, throughput, power consumption, and quality of service.

Storage system and method for inference of read thresholds based on memory parameters and conditions

A storage device includes a memory die and a controller. The controller identifies a dirty block that was subject to an interrupted I/O operation and performs a coarse inspection of the dirty block. Each iteration of the coarse inspection includes: requesting first bytes of a current page of the dirty block; receiving contents of the first bytes from the at least one memory die; and evaluating a state of the current page based on the contents of the first bytes. The controller also determines an initial last good page based on the coarse inspection and performs a fine inspection of at least one page based on a second number of bytes greater than the first number of bytes. The fine inspection validates the initial last good page and identifies the initial last good page as an actual last good page of the dirty block.

Systems and methods for improving find last good page processing in memory devices

The present disclosure generally relates to estimating when data to be written will be read or re-written prior to actually writing the data to the memory device. The estimating can be used to smartly route the data to the appropriate memory location at the writing stage or to evict the data from a hot memory location to a colder memory location. To perform the estimating, typical traces or data may be used as may the metadata of the data. Separating data according to the data 'temperature' (i.e. the expected access time and frequency), and usage to optimize the SLC partition usage has meaningful impact on several storage metrics such as performance and endurance.

Hot-cold chunks soft-prediction during programming

A system and method for calibrating read threshold voltages includes performing a plurality of read operations, determining to perform a read level tracking method, and performing the read level tracking method. The determining may be based on a temperature change or a bit error rate (BER). The read level tracking method includes determining the BER of an indicative word line, determining an adjusted read threshold level based on the BER, and adjusting read threshold levels according to the adjusted read threshold level.

Read threshold calibration for cross-temperature long, sequential reads

The disclosure relates in some aspects to on-chip processing circuitry formed within the die of a non-volatile (NVM) array to perform data searches. In some aspects, the die includes components configured to sense wordlines of stored data in the NVM array by applying voltages on the wordlines serially, and then search for an input data pattern within the serially-sensed wordlines. In some examples, the components of the die include latches and circuits configured to perform bitwise latch logic search operations. In other examples, the search components are configured with under-the-array or next-to-the-array dedicated search circuitry that uses registers and/or random access memory (RAM). Other aspects relate to a separate controller device for controlling the on-chip NVM search operations. For example, the controller may determine whether to search for data using search components of the NVM die or processors of the controller based, e.g., on a degree of fragmentation of data.

On-chip non-volatile memory (NVM) search

An apparatus includes a first encoder circuit configured to compress a block of data using dictionary based compression and a second encoder circuit connected to the first encoder circuit to receive the compressed block of data from the first encoder circuit. The second encoder circuit is configured to further compress the compressed block of data according to a codebook. The codebook is based on a distribution of data of a prior block of data or a distribution of data of a portion of the block of data that is less than the block of data. The operation of the second encoder circuit overlaps with the operation of the first encoder circuit to achieve high throughput and avoid the need for a large block of memory (e.g., SRAM) to occupy the data in flight until the second encoder circuit can start.

Data compression with entropy encoding

A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to determine a read threshold on a wordline, adjust a read threshold voltage level associated with the read threshold, determine an adjusted read threshold at the adjusted read threshold voltage level, where the adjusted read threshold is different from the read threshold, compare the adjusted read threshold to the read threshold, and calibrate the read threshold based on the comparing. The controller is further configured to analyze a bit error rate (BER) difference based on the calibrating and/or a previous read threshold voltage level movement, choose a next target read threshold for next calibration, and read a second page at the next target read threshold.

Read level tracking by random threshold movement with short feedback loop

Low-density parity-check (LDPC) coding based on memory cell voltage distribution (CVD) in data storage devices. In one embodiment, a memory controller includes a memory interface configured to interface with a non-volatile memory; and a controller. The controller is configured to receive a plurality of data pages to be stored in the non-volatile memory, and transform the plurality of data pages into a plurality of transformed data pages. The controller is further configured to determine a plurality of parity bits based on the plurality of transformed data pages, and store the plurality of data pages and the plurality of parity bits in the non-volatile memory.

Memory matched low density parity check coding schemes

A storage system has a memory with memory cells that can store a non-power-of-two number of states. A map is used to distribute data bits in the memory. The map can be a modified version of a quadrature amplitude modulation (QAM) map. The mapping can be done by a controller in the storage system or by the memory die. Performing the mapping in the memory die can reduce data traffic between the controller and the memory die, which can provide an improvement to performance and power consumption.

Storage system and method for multi-cell mapping

Interleaved ECC coding for key-value data storage devices. In one embodiment, a controller includes a memory interface including a namespace database; an ECC engine; a controller memory; and an electronic processor. The electronic processor is configured to receive a host write command, determine whether write access was setup as a key-value (KV) namespace in the namespace database and is associated with the host write command, and control the ECC engine and the memory interface to perform one or more program operations on the data in the memory using the interleaved ECC coding and based on the host write command in response to determining that the write access was setup as the KV namespace in the namespace database and the KV namespace is associated with the host write command.

Interleaved ECC coding for key-value data storage devices

A non-volatile memory system comprises an integrated memory assembly in communication with a memory controller. The integrated memory assembly includes a memory die bonded to a control die. The control die includes one or more control circuits for controlling the operation of the memory die. The control circuits are configured to receive a request to copy data on the memory die, read codewords on the memory die in response to the request, decode the codewords to identify errors in the codewords, correcting the errors in the codewords, and program the codewords back into the memory die. In one embodiment, the codewords read are stored in the memory die as single bit per memory cell data and the codewords programmed back into the memory die after correcting errors are programmed as multiple bit per memory cell data.

On-chip-copy for integrated memory assembly

Growing community of inventors

Rishon Lezion, Israel

Eran Sharon