Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Tel Aviv University

Sandisk Il Ltd.

Infineon Technologies Ag

Sandisk Corporation

Sandisk Ii, Ltd.

Eran Sharon

Idan Alrod

Alexander Bazarsky

Ariel Navon

Simon Litsyn

Ran Zamir

Dudy David Avraham

Omer Fainzilber

Stella Achtenberg

Menahem Lasser

Evgeny Mekhanik

Shay Benisty

Yan Li

Idan Goldenberg

Mark Murin

Ishai Ilani

Alon Eyal

Alex Bazarsky

Yehuda Hahn

Alon Marcu

Nima Mokhlesi

Dana Lee

Karin Inbar

Tz-Yi Liu

David Rozman

Tianhong Yan

Nika Yanuka

Mark Shlick

Tomer Tzvi Eliash

Rami Rom

Noam Presman

Liang Pang

Hadas Oshinsky

Tien-Chien Kuo

Yan Dumchin

Yuri Ryabinin

Ofer Shapira

Nian Niles Yang

Gerrit Jan Hemink

Raul-Adrian Cernea

Kevin M Conley

Toru Miwa

Rajeev Nagabhirava

Damian Pablo Yurzola

Joanna Lai

Sergey Anatolievich Gorobets

Seungjune Jeon

Amir Shaharabany

Grishma Shah

Julian Vlaiko

Jack Frayer

Tomer Eliash

Xinmiao Zhang

Opher Lieber

Yee Lih Koh

Arthur Shulkin

Nimrod Hermesh

Deepanshu Dutta

Christopher John Petti

Richard Leo Galbraith

Jianmin Huang

Itzhak Pomerantz

Yu-Chung Lien

David Robison Hall

Amit Kumar Sharma

Chris Avila

Gautam Ashok Dusija

Yoav Weinberg

Daniel Joseph Linnen

Preston Allen Thomson

Xinde Hu

Changyuan Chen

Kirubakaran Periyannan

Jonas Andrew Goode

Rohit Sehgal

Gadi Vishne

Gopinath Balakrishnan

Mai Ghaly

Marina Frid

Igor Genshaft

Refael Ben-Rubi

Abhinandan Venugopal

Arseniy Aharonov

Ofir Pele

Shahar Bar-Or

Vinayak Bhat

Rahav Yairi

Michael Micha Ionin

Asaf Gueta

Yossi Erlich

Yair Baram

Uri Peltz

Gen Pei

Wanfang Tsai

Henry Yip

Itshak Afriat

Lanlan Gu

Michal Silbermintz

A Harihara Sravan

Yigal Eli

A data storage device includes an error correction code (ECC) ordering system that determines a decoding schedule in which two or more flash memory units (FMUs) that have failed an initial decoding process are to be decoded using a joint decoding scheme. The ECC ordering system generates the decoding schedule based on a metric associated with each FMU. The metric on which the decoding schedule is based is a syndrome weight associated with each FMU or is a combined bit error rate (BER) associated with each FMU. When the decoding schedule has been generated, the ECC ordering system causes a joint decoding operation to be executed on the FMUs in the order specified by the decoding schedule.

Optimized decoding scheduling in a joint LDPC and RAID decoding scheme

A data storage device can generate a recommended read threshold value using a model that was trained under a plurality of conditions. However, such a model may result in an undesirable bit error rate or programming latency. If that should occur, the data storage device can use a different model trained under a condition similar to a current condition of the data storage device. In addition to avoiding an undesirable bit error rate or programming latency, this can result in improved throughput, improved quality of service, and reduced power consumption.

Data storage device and method for using multiple models for predicting a read threshold

A data storage device has an inference engine that can infer a read threshold based on a non-linear function of inputs that reflect current memory and data conditions. The read threshold can be used in reading a wordline in the memory. Using a machine-learning-based approach to infer a read threshold can provide significant improvement in read threshold accuracy, which can reduce bit error rate and also improve latency, throughput, power consumption, and quality of service.

Data storage device and method for inferring a read threshold using a time tag determination

Examples described herein provide a joint LDPC and XOR (JLX) error correction scheme that utilizes parity of the LDPC code to correct errors in XOR stripes of data, allowing improved protection against error. For example, when decoding of a codeword fails, an XOR operation is performed on the other codewords within the same XOR stripe to generate a copy of the failed codeword. The copy of the failed codeword is used as a soft bit input to an LDPC decoder, providing a sense of where errors in the failed codeword may be situated. The LDPC decoder may then recover the failed codeword. The scrambling seed used for encoding pages of data may also be used for recovering from error in a JLX ECC operation.

Data storage device with joint error correction code engines

A multi-gear ECC decoder includes a high power decoder and a low power decoder. In order to significantly reduce the decoding time for high-BER codewords using a slow high power decoder, rather than decoding codewords in either slow high power or fast low power, a controller switches between slow high power decoding and fast low power decoding during the decoding process. The controller first will determine, based on a predetermined factor, whether to start decoding in slow high power or fast low power. Once a decoding power is determined, then the decoding will begin. During the decoding process the decoding transitions from a first power lever decoder to a second power level decoder. The decoding will continue in the second decoding power level after the transition, until the decoding is completed or if another switch needs to occur for insufficient decoding.

ML assisted dynamic decoding gear selection

Before a read threshold is needed to read a wordline in memory, a data storage device can infer a plurality of read thresholds based on possible conditions of the memory that may exist when the read threshold is eventually needed. When the read threshold is needed, it is selected from the previously-inferred read thresholds based on the current conditions of the memory. This can improve latency and throughput, improve quality of service, reduce power consumption, and reduce errors.

Data storage device and method for predicting future read thresholds

A storage system has an inference engine that can infer a read threshold based on a plurality of parameters of the memory. The read threshold can be used in reading a wordline in the memory during a regular read operation or as part of an error handling process. Using a machine-learning-based approach to infer a read threshold can provide significant improvement in read threshold accuracy, which can reduce bit error rate and improve latency, throughput, power consumption, and quality of service. In another embodiment, a circuit-bounded array is used to manage updates to time and temperature tag information and to infer read thresholds.

Storage system and method for circuit-bounded-array-based time and temperature tag management and inference of read thresholds

A method and apparatus for systems and methods for digital signal processing (DSP) in a non-volatile memory (NVM) device comprising CMOS coupled to NVM die, of a data storage device. According to certain embodiments, one or more DSP calculations are provided by a controller to the CMOS components of the NVM, that configure one or more memory die to carry out atomic calculations on the data resident on the die. The results of calculations of each die are provided to an output latch for each die, back-propagating data back to the configured calculation portion as needed, otherwise forwarding the results to the controller. The controller aggregates the results of DSP calculations of each die and presents the results to the host system.

Enhanced digital signal processor (DSP) NAND flash

A shared decoder pool is susceptible to head-of-line blocking when the decoding of a given data block delays the decoding of other data blocks pipelined in the decoder. While the problem can be avoided by not using a pipeline operation, the benefits of pipelining would be lost. In one embodiment provided herein, the syndrome of an error pattern is calculated in parallel with data being written in an input buffer for the decoder. Parallelizing the syndrome calculation and the filling of the decoder's input buffer can avoid the head-of-line blocking problem noted above while still achieving the benefits of pipelining. In another embodiment, a similar technique is used in a bit error rate estimation scan (BES) operation. Other embodiments are provided.

Data storage device with efficient decoder pool and method for on-the-fly decoder initialization

For bit errors caused by intrinsic cell variations, the bit errors are scattered across a page of memory. However, for bit errors caused by a physical issue in memory, the bit errors cluster together within the same memory area. In an example data storage device, a page of memory is divided into sections, and counters are used to count the number of errors in each section. A physical error location is detected if the number exceeds a parameter, and as compared to the number of errors in the other sections. In another example data storage device having an error correction code (ECC) engine, a histogram and binomial probability are used to detect physical errors. This has the advantage of detecting weak memory blocks that are about to fail, so the blocks can be retired early as a grown bad block.

Data storage device and method for identifying a failing area of memory based on a cluster of bit errors

A storage system has an inference engine that can infer a read threshold based on a plurality of parameters of the memory. The read threshold can be used in reading a wordline in the memory during a regular read operation or as part of an error handling process. Using this machine-learning-based approach to infer a read threshold can provide significant improvement in read threshold accuracy, which can reduce bit error rate and improve latency, throughput, power consumption, and quality of service. In another embodiment, a storage system is configured to use a binary full-depth symmetrically-sorted tree to infer a read threshold based on a plurality of parameters of the memory.

Storage system and method for implementation of symmetric tree models for read threshold calibration

Methods and apparatus for power management in data storage devices are provided. One such data storage device (DSD) includes a non-volatile memory (NVM), a set of hardware processing engines, and a power sensor to detect a total power consumption of the set of hardware processing engines. A processor is configured to determine a power-per-processing event value for each of the set of processing engines based on total power consumption measurements, then control delivery of power to the processing engines based on the power-per-processing event values in accordance with a power budget. In some examples, the DSD employs a least-squares procedure to estimate the power-per-processing event values so the values can be determined without needing to measure the individual power consumption of the processing engines. Exemplary processing engines include a Read engine, a Write engine, etc. A recursive least-squares update procedure is also described.

Power-per-processing event estimates based on total power consumption measurements within a data storage device

A storage system has an inference engine that can infer a read threshold based on a plurality of parameters of the memory. The read threshold can be used in reading a wordline in the memory during a regular read operation or as part of an error handling process. Using this machine-learning-based approach to infer a read threshold can provide significant improvement in read threshold accuracy, which can reduce bit error rate and improve latency, throughput, power consumption, and quality of service.

Storage system and method for inference of read thresholds based on memory parameters and conditions

A storage device includes a memory die and a controller. The controller identifies a dirty block that was subject to an interrupted I/O operation and performs a coarse inspection of the dirty block. Each iteration of the coarse inspection includes: requesting first bytes of a current page of the dirty block; receiving contents of the first bytes from the at least one memory die; and evaluating a state of the current page based on the contents of the first bytes. The controller also determines an initial last good page based on the coarse inspection and performs a fine inspection of at least one page based on a second number of bytes greater than the first number of bytes. The fine inspection validates the initial last good page and identifies the initial last good page as an actual last good page of the dirty block.

Systems and methods for improving find last good page processing in memory devices

The present disclosure generally relates to estimating when data to be written will be read or re-written prior to actually writing the data to the memory device. The estimating can be used to smartly route the data to the appropriate memory location at the writing stage or to evict the data from a hot memory location to a colder memory location. To perform the estimating, typical traces or data may be used as may the metadata of the data. Separating data according to the data 'temperature' (i.e. the expected access time and frequency), and usage to optimize the SLC partition usage has meaningful impact on several storage metrics such as performance and endurance.

Hot-cold chunks soft-prediction during programming

Growing community of inventors

Rishon Lezion, Israel

Eran Sharon