Marvell Israel (misl) Ltd.

Chip Express (israel) Ltd.

Marvell Semiconductor Israel Ltd.

Quick Technologies Ltd.

Eran Rotem

Uzi Yoeli

Zvi Orbach

Meir I Janai

Rami Zemach

Itay Peled

Yehuda Yizraeli

Richard Stephen Phillips

Aspects of the disclosure provide an integrated circuit (IC) that is configured to have an increased yield. The IC includes a memory element configured to store a specific value determined based on a characteristic of the IC, and a controller configured to control an input regulator based on the specific value of the IC. The input regulator is operative to provide a regulated input to the IC during operation, such that the IC performance satisfies performance requirement.

Controllably adjusting voltage for operating an integrated circuit within specified limits

Aspects of the disclosure provide a method for semiconductor wafer manufacturing. The method includes utilizing a subset of lower level masks in a mask set to form multiple modular units of lower level circuit structures on a semiconductor wafer. The mask set includes the subset of lower level masks and at least a first subset of upper level masks and a second subset of upper level masks. The first subset of upper level masks defines intra-unit interconnections. The second subset of upper level masks defines both intra-unit interconnections and inter-unit interconnections. The method further includes selecting one of at least the first subset of upper level masks and the second subset of upper level masks based on a composition request of a final integrated circuit (IC) product and utilizing the selected subset of upper level masks to form upper level structures on the semiconductor wafer.

Method to produce a semiconductor wafer for versatile products

Systems and methods are provided for an integrated circuit package. A plurality of electrical contacts are configured to provide a structure for electrically connecting the integrated circuit package to a printed circuit board. A package substrate includes at least one patterned metallic layer formed to electrically interconnect I/O contacts of an integrated circuit to the plurality of electrical contacts, and at least one generally uniform metallic layer having a plurality of voids that are respectively situated in axial alignment with corresponding ones of the electrical contacts, and one or more dielectric layers disposed between the plurality of electrical contacts and the metallic layers. Further, the package substrate includes a plurality of metallic elements disposed within the plurality of voids and electrically isolated from the generally uniform metallic layer, the metallic elements configured to reduce a physical size of respective voids without electrically contacting the generally uniform metallic layer.

Systems and methods for mechanical and electrical package substrate issue mitigation

Systems and methods for mitigation of mechanical degradation in high performance electrical circuit packages

Method and apparatus for increasing yield

A method of forming a flip chip device comprises providing a semiconductor die having a core area and a periphery area. The periphery area includes an electrostatic discharge (ESD) structure. The semiconductor die including includes at least one power conductor. A substrate having a source of power is provided. A first connection circuit is located within the semiconductor die core area to couple power between the substrate and the semiconductor die power conductor. The ESD structure is electrically coupled to the first connection circuit. The first connection circuit is electrically coupled to the substrate via a conductive bump.

Flip chip with novel power and ground arrangement

A flip chip assembly comprising a semiconductor die having a core area and a periphery area. The periphery area including an ESD structure. The semiconductor die includes at least one power conductor to supply power between the core area and the periphery. A substrate is coupled to the semiconductor die via a plurality of electrically conductive bumps. A first connection circuit is located within the semiconductor die core area to couple power between the substrate and the semiconductor die power conductor. An electrically conductive bump provides a connection between the first connection circuit and the substrate. The ESD structure is coupled to the first connection circuit.

A customizable gate array device including a customizable gate array portion and a customizable memory portion.

Customizable integrated circuit device

A customizable logic array device including an array of identical multiple input, function selectable logic cells comprising a first conductive layer, application configurable interconnection apparatus selectably interconnecting the multiple input, function selectable logic cells, the application configurable interconnection apparatus comprising at least two conductive layers.

Customizable logic array device

A very high speed customizable logic array device comprising:

High speed customizable logic array device

A cell forming part of a customizable logic array and including at least first and second different multiplexers, an output of the first multiplexer being connected to an input of the second multiplexer.

Growing community of inventors

Haifa, Israel

Eran Rotem