Motorola Corporation

Freescale Semiconductor,inc.

Eran Pisek

Moshe Tarrab

Thomas J Kundmann

Eytan Engel

Mack Mansouri

Yossi Amon

Jacob Tokar

Mark Elnekave

David Moshe

A device and method for performing SISO decoding. The method comprising the steps of: (a) providing a trellis representative of an output of a convolutional encoder, the convolutional encoder has a coding rate of R, the trellis having a block length T. (b) assigning an initial conditions to each starting node of the trellis for a forward iteration through the trellis. (c) computing a forward metric for each node, starting from the start of the trellis and advancing forward through the trellis and storing forward metrics of nodes of a plurality of starting stages of windows. (d) repeating stages d(1)-d(3) until all lambdas of the trellis are calculated; d(1) retrieving forward metrics of nodes of a starting stage of a window, the retrieved forward metrics were computed and stored during step (c). d(2) computing and storing forward metrics for each node, starting from a second stage of the window and ending at the ending stage of the window. d(3) computing backward metrics for each node, starting from the ending stage of the window and ending at the starting stage of the window; wherein when backward metrics of nodes of a stage are computed and the forward metrics of the nodes of an adjacent stage were previously computed, the computation of backward metrics is integrated with the computation of lambda from the stage to the adjacent stage and a storage of the calculated lambdas.

Apparatus and method for performing SISO decoding

A filter comprising of an internal memory for storing data and coefficients; an address generation unit, for generating memory addresses; a multiply and accumulate unit (i.e.&mdash;MAC unit), for performing multiply and accumulate functions. The filter can operate in a plurality of modes, such as multiple or single channel FIR filtering; multiple or single channel IIR filtering; multiple or single channel echo cancellation; multiple or single channel decimation and multiple or single channel extrapolation.

Multi channel filtering device and method

An electronic apparatus receives a noisy signal and produces and stores hard data and soft data. It has a first portion ( ) for receiving electromagnetic signals and producing hard data and soft data, and a second portion ( ) for storing soft data and hard data concerning a particular signal at a single location in a memory bank ( ), preferably at the same memory address. Hard data and soft data can be stored in consecutive memory cells. Hard data can overlap soft data. If hard data overlaps soft data, it preferably overlaps soft data least significant bits. The second portion ( ) has a memory bank ( ), a controller ( ) and also can have a synchronizer ( ) for synchronizing between soft data and hard data concerning the same input signal.

Electronic apparatus and method for receiving noisy signals

A finite impulse response filter (,) has a data memory bank (,) for storing data vectors and a coefficient memory bank (,) for storing coefficient vectors. Filtering is done by multiplying data words by coefficient words, and summing the results. The finite impulse response filter (,) operates in different modes, according to the type of data vector and coefficient vector. In two modes of operation consecutive elements of the data vector (,) are stored in consecutive odd memory words (,) within the data memory bank (,). In other modes consecutive elements of the data vector are stored in consecutive memory words (,) in the data memory bank (,). Consecutive coefficient vector elements (,) are stored in the consecutive memory words (,) in coefficient memory bank (,), wherein coefficient elements can be stored in reverse or forward order. The data memory bank (,) is coupled to a data address generator (,) comprising of counter (,), two multiplexers (,), a XOR gate (,) and an AND gate (,).

Finite impulse response filter and method

A filter co-processor within a Digital Signal Processor (DSP) takes advantage of the orthogonal nature of modulated signals during the equalization process. Since, after reception, only certain real/imaginary values of the received signal are useful for demodulation, the filter co-processor only processes those values to estimate the transmitted signal. By processing only those values useful for demodulation, the filter co-processor is able to process more information in a given amount of time, leading to increased processing when compared to the prior art.

Growing community of inventors

Holon, Israel

Eran Pisek