Intel Corporation

Mplicity Ltd.

Eran Dagan

Efraim Rotem

Amit Bleiweiss

Amit Gur

Gil Vinitzky

Anat Heilper

Boris Mishori

In one embodiment, a field programmable gate array (FPGA) includes: at least one programmable logic circuit to execute a function programmed with a bitstream; a self-test circuit to execute a self-test at a first voltage, the self-test and the first voltage programmed with first metadata associated with the bitstream, the self-test including at least one critical path length of the function; and a power controller to identify an operating voltage for the at least one programmable logic circuit based at least in part on the execution of the self-test at the first voltage.

System, apparatus and method for adaptive operating voltage in a field programmable gate array (FPGA)

Apparatus, devices, systems, methods, and articles of manufacture are disclosed to allocate power in a computing device. An example system includes a compiler to: analyze power consumption behavior of power consumption units of the computing device; build a power profile; and generate source code with hints of the power profile. The example system includes a power control circuit to: develop a power policy using the hints of the power profile and requests for power licenses from the power consumption units of the computing device; and allocate power to the power consumption units based on the power profile.

Compiler guided power allocation in computing devices

A method for circuit design includes performing a timing analysis of a design of a processing stage in an integrated electronic circuit, and specifying a cycle time of the circuit. Responsively to the cycle time and to the timing analysis, a window is identifying within the processing stage containing a set of connection points among the circuit components at which the processing stage may be split for addition of multithreading capability to the circuit. A subset of the connection points is selected, and splitter components are inserted at the connection points in the subset.

Chip area optimization for multithreaded designs

Growing community of inventors

Tel Aviv, Israel

Eran Dagan