Apple Inc.

Era K Nangia

Farid Nemati

Gregory S Mathews

Bernard Joseph Semeria

James Vash

Derek R Kumar

Steven R Hutsell

Techniques are disclosed relating to memory error tracking and logging. In some embodiments, a memory cache controller circuitry is configured to track, using multiple circuit entries, numbers of detected correctable errors associated with multiple respective locations, and in response to detecting a threshold number of correctable errors for a particular location, generate a signal to the one or more processors that identifies the particular location. In some embodiments, the memory cache controller circuitry includes multiple circuit entries for tracking uncorrectable errors.

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Los Altos, CA, United States of America

Era K Nangia