Au Optronics Corporation

Er-Lang Deng

Wei-Kai Huang

Chia-Heng Chen

Cheng-Hung Ko

Yi-Fu Chen

You-Ying Lin

Yuan-Nan Chiu

Hsiao-Chun Chen

Shin-Shian Lee

Yu-Lin Huang

I-Sheng Lin

Kuo-Ting Yang

Chih-Yuan Wu

A gate driving circuit comprises a plurality of shift registers coupled in serial. An nth shift register includes a driving circuit, a pull-up circuit and a first auxiliary voltage regulator circuit. The driving circuit is electrically coupled to an output node and a first node. The driving circuit is configured to receive a clock signal and output a gate signal according to the clock signal. The pull-up circuit is electrically coupled to the driving circuit. The first auxiliary voltage regulator circuit is electrically coupled to the pull-up circuit and a second node. The first auxiliary voltage regulator circuit is configured to receive a control signal and the second node corresponding to a second voltage.

Gate driving circuit and shift register controlling method

A driving circuit including an output circuit, a pull-down module, conductive wires, at least one first signal line, and a buffer layer is provided. The conductive wires are electrically connected between the output circuit and the pull-down module. The output circuit and the pull-down module are electrically coupled to a driving control signal through the first signal line. A first overlapping region is located between the first signal line and a portion of the conductive wires. The buffer layer is disposed between the first signal line and the portion of the conductive wires. The buffer layer includes an overlapping portion and an extending portion. The overlapping portion is at least disposed in the first overlapping region. The extending portion is disposed outside the overlapping portion. A thickness of the overlapping portion is greater than a thickness of the extending portion. A display panel is also provided.

Driving circuit and display panel

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Hsin-Chu, Taiwan

Er-Lang Deng