Samsung Electronics Co., Ltd.

Eon Soo Jang

Yunhyeok Im

Kyol Park

Kyung Suk Oh

Jae Choon Kim

Jichul Kim

Eunseok Song

Keung Beum Kim

Manho Lee

Jongwoo Park

Soojae Park

Jin-Kwon Bae

Heejung Hwang

Woo Hyun Park

Young Sang Cho

A semiconductor package including a first semiconductor chip including a logic structure and a second semiconductor chip bonded to the first semiconductor chip may be provided. The first semiconductor chip may include signal lines on a first surface of a first semiconductor substrate and connected to the logic structure, a power delivery network on a second surface of the first semiconductor substrate, the second surface being opposite to the first surface, and penetration vias penetrating the first semiconductor substrate and connecting the power delivery network to the logic structure. The second semiconductor chip may include a capacitor layer that is on a second semiconductor substrate and is adjacent to the power delivery network.

Semiconductor package

A semiconductor package includes a semiconductor chip having a first surface that is an active surface and a second surface opposing the first surface, a first redistribution portion disposed on the first surface, the first redistribution portion including a lower wiring layer electrically connected to the semiconductor chip, a thermal conductive layer disposed on the second surface of the semiconductor chip, a sealing layer surrounding a side surface of the semiconductor chip and a side surface of the thermal conductive layer, and a second redistribution portion disposed on the sealing layer, the second redistribution portion including a first upper wiring layer connected to the thermal conductive layer, the second redistribution portion including a second upper wiring layer electrically connected to the semiconductor chip.

Semiconductor package including a thermal conductive layer and method of manufacturing the same

A semiconductor package includes a lower package with a lower substrate and a lower semiconductor chip. A heat dissipation part is provided adjacent to a side of the lower package and covers a portion of the lower semiconductor chip, and an upper package is on the lower package and is laterally spaced apart from the heat dissipation part.

Semiconductor packages including upper and lower packages and heat dissipation parts

A semiconductor package includes a semiconductor chip on a package substrate, a heat spreader on the semiconductor chip, a molding layer, an adhesive film between the semiconductor chip and the heat spreader, and a through-hole passing through the heat spreader. The heat spreader includes a first surface and a second surface. The molding layer covers sidewalls of the semiconductor chip and the heat spreader and exposes the first surface of the heat spreader. The adhesive film is on the second surface of the heat spreader.

Semiconductor package including heat spreader and method for manufacturing the same

The inventive concepts provide package-on-package (PoP) devices. In the PoP devices, an interposer substrate and a thermal boundary material layer may be disposed between a lower semiconductor package and an upper semiconductor package to rapidly exhaust heat generated from a lower semiconductor chip included in the lower semiconductor package. The interposer substrate may be formed of one or more insulating layers, conductive vias, heat dissipating members, protection layers, and various conductive patterns.

Package-on-package device

According to example embodiments, a semiconductor package includes a lower package, upper packages on the lower package and laterally spaced apart from each other, a lower heat exhaust part between the lower package and the upper packages, an intermediate heat exhaust part between the upper packages and connected to the lower heat exhaust part, and an upper heat exhaust part on the upper packages and connected to the intermediate heat exhaust part.

Semiconductor packages including heat exhaust part

A semiconductor package includes a substrate. A lower semiconductor chip is disposed above the substrate. An upper semiconductor chip is disposed on the lower semiconductor chip. A top surface of the lower semiconductor chip at an end of the lower semiconductor chip is exposed. A heat slug disposed above the upper semiconductor chip. A molding layer is disposed between the substrate and the heat slug. The molding layer is configured to seal the lower semiconductor chip and the upper semiconductor chip. An upper spacer is disposed between the lower semiconductor chip and the heat slug. The upper spacer is disposed on the exposed surface of the lower semiconductor chip.

Semiconductor package having a heat slug and a spacer

A semiconductor package device includes a lower package including a lower semiconductor chip mounted on the lower package substrate, a lower molding compound layer disposed on the lower package substrate, a first trench formed in the lower molding compound layer to surround the lower semiconductor chip, and a second trench connected to the first trench to extend to an outer wall of the lower package, the second trench being formed in the lower molding compound layer, an upper package disposed on the lower package. The upper package includes an upper package substrate and at least one upper semiconductor chip mounted on the upper package substrate and a heat transfer member disposed between the lower package and the upper package.

Growing community of inventors

Suwon-si, South Korea

Eon Soo Jang