Samsung Electronics Co., Ltd.

Seoul National University

Skhynix Inc.

Eojin Lee

Jungho Ahn

Jaehyun Park

Sunjung Lee

Jaewan Choi

Byeongho Kim

Wonkyung Jung

Minbok Wi

Jongwook Chung

Seungwoo Seo

Yuhwan Ro

Jaewook Lee

Woosuk Kwon

Taehyung Kim

Jung Ho Ahn

Daeyoung Moon

Hoon Shin

Hoyoung Tang

Taejun Ham

Yeonhong Park

Ingab Kang

A dual-port static random access memory (SRAM) cell is provided. The dual-port SRAM cell includes: P-type active patterns that are spaced apart from one another along a first direction, each of the P-type active patterns extending in a second direction perpendicular to the first direction and including at least one transistor. The P-type active patterns include first through sixth P-type active patterns which are sequentially arranged along the first direction. A first cutting area is provided between the second P-type active pattern and a first boundary of the dual-port SRAM cell that extends along the first direction, and a second cutting area is provided between the fifth P-type active pattern and a second boundary that is opposite to the first boundary and extends along the first direction.

Dual port SRAM cell and method of designing the same

A processor-implemented data processing method includes: generating compressed data of first matrix data based on information of a distance between valid elements included in the first matrix data; fetching second matrix data based on the compressed data; and generating output matrix data based on the compressed data and the second matrix data.

Method and apparatus with data processing

A semiconductor memory device includes a plurality of memory banks including a first memory bank group including a computation circuit and a second memory bank group without a computation circuit; and a control circuit configured to control a PIM operation by the first memory bank group to be performed together with processing of memory requests for the plurality of memory banks while satisfying a maximum power consumption condition of the semiconductor memory device.

Semiconductor memory device employing processing in memory (PIM) and operation method of the semiconductor memory device

A hammer refresh row address detector includes a control logic unit that receives a row address applied along with an active command, to increase a hit count stored in a corresponding entry when the row address is present in candidate aggressor row addresses stored in n entries. The control logic determines a candidate aggressor row address stored in an entry in which the hit count equals a threshold value to be a target aggressor row address. The control logic generates a victim row address adjacent to the target aggressor row address as a hammer refresh row address to accompany a hammer refresh command. The control logic increases the miss count value when the row address is not present in the candidate aggressor row addresses stored in the n entries and no hit count within the n entries is identical to the miss count value.

Hammer refresh row address detector, and semiconductor memory device and memory module including the same

A row hammer prevention circuit for providing a reference address to perform an additional refresh operation includes a history storage circuit configured to store one or more first addresses, each of the first addresses having been provided as the reference address. The row hammer prevention circuit further includes an address storage circuit configured to store a row address corresponding to an active command, a reference address storage circuit configured to store one or more second addresses, and a control circuit configured to provide the reference address in response to a refresh command.

Row hammer prevention circuit, a memory module including the row hammer prevention circuit, and a memory system including the memory module

Growing community of inventors

Suwon-si, South Korea

Eojin Lee