Infineon Technologies Austria Ag

Infineon Technologies Dresden Gmbh & Co . Kg

Enrique Vecino Vazquez

Franz Hirler

Christian Fachmann

Armin Willmeroth

Joachim Weyers

Manfred Pippan

Patrick Schindler

Daniel Pobig

Ahmed Mahmoud

Winfried Kaindl

Gabor Mezoesi

Katarzyna Kowalik-Seidl

Andreas Schloegl

Yann Ruet

Andreas Boehm

Katarzyna Kowalik Seidl

A semiconductor device includes transistor cells formed along a first surface at a front side of a semiconductor body and having body regions of a first conductivity type, a drift region of a second conductivity type that is opposite from the first conductivity type and is disposed between the body regions and a second surface of the semiconductor body that is opposite from the first surface, and an emitter layer of the second conductivity type that is disposed between the drift region and a second surface of the semiconductor body, the emitter layer having a higher dopant concentration than the drift region, a metal drain electrode directly adjoining the emitter layer. The metal drain electrode comprises spikes extending into the emitter layer.

Semiconductor device with drain structure and metal drain electrode

A semiconductor device includes a semiconductor body comprising a first surface, a second surface opposite to the first surface, an active region, and an edge region surrounding the active region in a horizontal plane. The semiconductor device further includes a plurality of transistor cells at least partly integrated in the active region. Each transistor cell includes a drift region separated from a source region by a body region, and a gate electrode dielectrically insulated from the body region. The semiconductor device also includes a sensor device having a first sensor region of a first doping type integrated in the edge region. The first sensor region is electrically coupled to a first contact pad and to a second contact pad. Each contact pad is arranged either on the first surface or on the second surface. The sensor device at least partially extends around the active region.

Semiconductor device with sensor for crack detection

A transistor device includes transistor cells each having source and drift regions of a first doping type and a body region of a second doping type in a first region of a semiconductor body, and a gate electrode dielectrically insulated from the body region. A gate conductor arranged on top of a second region of the semiconductor body is electrically connected to each gate electrode. A source conductor arranged on top of the first region is connected to each source and body region. A discharging region of the second doping type is arranged in the second region and located at least partially below the gate conductor, and includes at least one lower dose section in which a doping dose is lower than a minimum doping dose in other sections of the discharging region. The at least one lower dose section is associated with a corner of the gate conductor.

Vertical transistor device having a discharge region comprising at least one lower dose section and located at least partially below a gate electrode pad

According to an embodiment of a semiconductor device, the semiconductor device includes: transistor cells formed along a first surface at a front side of a semiconductor portion; a drain structure between the transistor cells and a second surface of the semiconductor portion opposite to the first surface, the drain structure forming first pn junctions with body regions of the transistor cells and including an emitter layer directly adjoining the second surface; and a metal drain electrode directly adjoining the emitter layer. An integrated concentration of activated dopants along a shortest line between the metal drain electrode and a closest doped region of a charge type of the body regions is at most 1.5E13 cm. Further semiconductor device embodiments are described.

A semiconductor device includes a semiconductor body. The semiconductor body has a first surface and a second surface opposite to the first surface. A transistor cell structure is provided in the semiconductor body. A gate contact structure includes a gate line electrically coupled to a gate electrode layer of the transistor cell structure, and a gate pad electrically coupled to the gate line. A gate resistor structure is electrically coupled between the gate pad and the gate electrode layer. An electric resistivity of the gate resistor structure is greater than the electric resistivity of the gate electrode layer.

Semiconductor device including a gate contact structure

A semiconductor device includes a transistor arrangement and a diode structure. The diode structure is coupled between a gate electrode structure of the transistor arrangement and a source electrode structure of the transistor arrangement. An insulating layer is located vertically between the diode structure and a front side surface of a semiconductor substrate of the semiconductor device. The diode structure includes at least one diode pn-junction. A substrate pn-junction extends from the front side surface of the semiconductor substrate into the semiconductor substrate between a shielding doping region and an edge doping portion. The edge doping portion is located adjacent to the shielding doping region within the semiconductor substrate. At the front side surface of the semiconductor substrate, the substrate pn-junction is located laterally between the diode pn-junction and a source contact region of the diode structure with the source electrode structure.

Semiconductor devices and methods for forming a semiconductor device

Disclosed is a transistor device. The transistor device includes: a semiconductor body with an active region and a pad region; at least one transistor cell including a gate electrode dielectrically insulated from a body region by a gate dielectric, wherein the body region is arranged in the active region; an electrode layer arranged above the pad region and dielectrically insulated from the pad region by a further dielectric; and a gate pad arranged above the electrode layer and electrically connected to the electrode layer and the gate electrode of the at least one transistor cell. A thickness of the further dielectric is equal to or less than a thickness of the gate dielectric.

Transistor device with increased gate-drain capacitance

An epitaxial layer is formed by epitaxy on a base substrate at a front side. From opposite to the front side, at least a portion of the base substrate is removed, wherein the base substrate is completely removed or a remnant base section has a thickness of at most 20 &#x3bc;m. Dopants of a first charge type are implanted from opposite of the front side into an implant layer of the epitaxial layer. A metal drain electrode is formed opposite to the front side. At least the implant layer is heated to a temperature not higher than 500&#xb0; C. The heating activates only a portion of the implanted dopants in the implant layer. After heating, an integrated concentration of activated dopants along a shortest line between the metal drain electrode and a closest doped region of a second, complementary charge type is at most 1.5E13 cm.

Semiconductor device with drift zone and backside emitter and method of manufacturing thereof

In accordance with an embodiment, a method of operating a semiconductor switch coupled to an inductor includes turning on the semiconductor switch by applying a turn-on voltage to between a gate of the semiconductor switch and a low current terminal connected to a reference node of the semiconductor switch, the low current terminal separate from a high current reference terminal connected to the reference node of the semiconductor switch, and the semiconductor switch comprises a first input capacitance to transconductance ratio. The method further includes turning off the semiconductor switch by applying a turn-off voltage to the gate of the semiconductor switch, wherein a ratio of a total capacitance at an output node of the semiconductor switch to a gate-drain capacitance is greater than a first ratio per watt of power being handled by a load coupled to the semiconductor switch.

System and method for a switching transistor

A semiconductor device includes a semiconductor substrate having an outer rim, a plurality of switchable cells defining an active area, and an edge termination region arranged between the switchable cells and the outer rim. Each of the switchable cells includes a gate electrode structure. The semiconductor device further includes a gate metallization in contact with the gate electrode structure. The active area includes at least a first switchable region having a first specific transconductance and at least a second switchable region having a second specific transconductance which is different from the first specific transconductance. The second switchable region is arranged between the gate metallization and the first switchable region. A ratio of the area of the second switchable region to the total area of the switchable regions is in a range from 5% to 50%.

Semiconductor device having switchable regions with different transconductances

A method for manufacturing a semiconductor device includes providing a semiconductor substrate having an outer rim, an active area, and an edge termination region arranged between the active area and the outer rim, and forming a plurality of switchable cells in the active area. Each of the switchable cells includes a body region, a gate electrode structure, and a source region. The active area defined by the switchable cells includes at least a first switchable region having a specific gate-drain capacitance which is different to a specific gate-drain capacitance of a second switchable region. The method further includes forming a source metallization in ohmic contact with the source regions of the switchable cells, and forming a gate metallization in ohmic contact with the gate electrode structures of the switchable cells.

Method for manufacturing a semiconductor switching device with different local cell geometry

A semiconductor device includes a semiconductor substrate having a plurality of switchable cells defining an active area of the semiconductor device, an outer rim, and an edge termination region arranged between the switchable cells and the outer rim. Each of the switchable cells includes a body region, a gate electrode structure and a source region. A source metallization is in ohmic contact with the source regions of the switchable cells. A a gate metallization is in ohmic contact with the gate electrode structures of the switchable cells. The active area defined by the switchable cells includes at least a first switchable region having a first threshold and at least a second switchable region having a second threshold which is higher than the first threshold. An area assumed by the first switchable region is larger than an area assumed by the second switchable region.

Semiconductor switching device with different local threshold voltage

A semiconductor device includes a semiconductor substrate having an outer rim, a plurality of switchable cells defining an active area, and an edge termination region arranged between the switchable cells defining the active area and the outer rim. Each of the switchable cells includes a body region, a gate electrode structure and a source region. The active area defined by the switchable cells includes at least a first switchable region having a first transconductance and a second switchable region having a second transconductance which is different from the first transconductance.

Semiconductor switching devices with different local transconductance

A semiconductor device includes a semiconductor substrate having an outer rim, a plurality of switchable cells defining an active area, and an edge termination region arranged between the switchable cells defining the active area and the outer rim. Each of the switchable cells includes a body region, a gate electrode structure and a source region. A source metallization is in ohmic contact with the source regions of the switchable cells. A gate metallization is in ohmic contact with the gate electrode structures of the switchable cells. The active area defined by the switchable cells includes at least a first switchable region having a specific gate-drain capacitance which is different to a specific gate-drain capacitance of a second switchable region.

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Munich, Germany

Enrique Vecino Vazquez