Advanced Micro Devices Corporation

Enrique Rendon

Tahsin Askar

Paul W Berndt

Mike Lowe

Hamilton B Carter

Jelena Ilic

Mark LaVine

A system and method for memory incoherent verification of functionality of an HDL (Hardware Description Language) design of a computer system component is disclosed. A simulated model of the HDL design receives a memory read stimulus from a stimulus file through a simulated first bus. The simulated model of the HDL design is configured to send its response to the stimulus onto a simulated second bus. A transaction checker receives the response from the simulated second bus and analyzes it to verify operation of the HDL design of the computer system component. The stimulus file and the transaction checker are both stored in the computer system memory. The simulated model's response to the memory read stimulus is evaluated by the transaction checker independently of any previous memory write stimulus from the stimulus file. There is no need to have a previous memory write operation or a master initialization of the system memory for every memory read operation. This enhances the sequences of operations that may be applied to a device under test. Multiple simulated models may read or write into the memory without timing constraints.

Memory incoherent verification methodology

A verification system and method for verifying operation of an HDL (Hardware Description Language) design of a computer system component are disclosed. The computer system is configured to interface between a first bus and second bus. During verification, a simulated model of the HDL design is coupled to a simulated first bus and a simulated second bus. A designated stimulus is applied to the simulated model through the simulated first bus. A stimulus file stored in the computer system memory is configured to specify the designated stimulus to be applied. In response to the designated stimulus, the simulated model initiates bus cycles on the simulated second bus. A transaction checker is provided in the computer system memory to receive information relating to these bus cycles from said simulated second bus. By employing two different busses--one to apply a stimulus and the other to resolve the bus cycle through transaction checking--an effective decoupling of test stimulus from the checking environment is achieved. Due to decoupling, the test environment can be made more robust, and can be used to generate random responses, remap memory, inject errors into data streams etc.

Verification strategy using external behavior modeling

A system and method for dynamic verification of functionality of an HDL (Hardware Description Language) design of a computer system component is disclosed. A simulated model of the HDL design is created. A test configuration for the simulated model is selected through a configuration interpretation mechanism, based on a plurality of user-supplied parameters. The user-supplied parameters, for example, include the amount of the memory in the system, the number of memory banks, addresses of various PCI devices, the type of the CPU etc. The test configuration is then compiled. At run-time, the test configuration is simulated. The responses by the simulated model of the HDL design to various test stimuli from a stimulus file are then evaluated under the chosen test configuration. One or more different test configurations may be simulated at run-time, and the stimulated model's responses to a pre-determined set of test stimuli may be reevaluated for each such test configuration. Thus, the test configuration is effectively separated from the test stimulus generation mechanism. This allows permutations of a given test suite across many test configurations without creating extremely large number of tests.

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Pflugerville, TX, United States of America

Enrique Rendon