Motorola Corporation

Freescale Semiconductor,inc.

Enrique Ferrer

Raul Salvi

Keith Andrew Tilley

Edward T Clark

Kenneth A Hansen

Robert E Stengel

Charles R Ruelke

Joseph P Heck

Kevin B Traylor

Olin L Hartin

Radu Mircea Secareanu

David L Muri

David J Graham

Ralph T Enderby

Wayne P Shepherd

Suman K Banerjee

Rajesh H Zele

Atif A Meraj

James C Goatley

Andrew J Webster

Charles M Schlosser

A system-on chip (SOC) () and method of isolating noise in a SOC, including a plurality of noise sensitive circuit blocks () and ESD protected pads (and). A VDD isolation pad () is connected to an N well ring () of the first noise sensitive circuit () to collect noise from the substrate () and isolate the circuit from the P well region (). A ground protected pad () is connected to an isolated P well () of a first noise sensitive circuit (). The ground pad () collects noise from the isolated P well () and sends it to ground. A dedicated ground isolation pad () is connected to a P well ring () of a second noise sensitive circuit (). The dedicated ground isolation pad () collects noise from the P well ring () and sends it to ground. The dedicated ground isolation pad () and the ground pad () collect noise that would normally propagate between the first and second noise sensitive circuits () and additional circuits that share the same substrate ().

Integrated circuit with improved signal noise isolation and method for improving signal noise isolation

A DC offset correction method and apparatus. In a DC offset correction loop ( ), a DC offset is corrected using a binary search routine or any other digital or analog DC offset correction technique. In this binary search routine, the sign of the offset ( ) is used to control a direction in which a digital to analog converter (DAC) ( ) is stepped until the least significant bit of the DAC is set. The process is enhanced by opening up the bandwidth of the baseband filters ( ) to permit the binary search to be clocked ( ) at a higher clock rate. After the correction is established, the filters ( ) are reset to normal operating conditions.

Enhanced DC offset correction through bandwidth and clock speed selection

A DC offset correction method and apparatus. Several DC offset correction schemes including a digital binary search scheme (,), a digital slow averaging scheme (,) and an analog integration (,) scheme are provided. A controller (,) selects one or more of the correction schemes in accordance with the desired characteristics provided by each scheme.

DC offset correction adaptable to multiple requirements

A DC offset correction loop (,) utilizes a sign bit generator (,), binary search stage (,), and a digital-to-analog converter (,) in its feedback path to correct for DC offsets at the input of a gain stage (,). When a correction value is obtained, it is applied and held (,) to compensate for the DC offset. When a programming event occurs (,), such as detecting an increase in DC offset beyond a threshold, detecting a significant temperature change, or passage of time, a new DC offset correction cycle is initiated.

Method and apparatus for settling and maintaining a DC offset

A DC offset correction loop (200) utilizes a sign bit generator (204), binary search stage (206), and a digital-to-analog converter (208) in its feedback path to correct for DC offsets at the input of a gain stage (202).

Method and apparatus for settling a DC offset

A SONAD (110) control system (100) detects a received signal strength (RSSI) for a radio frequency (RF) signal (102), selects a threshold transfer function (400-404) in response thereto, generates a threshold control signal in response to the transfer function, and utilizes the threshold control signal to select the SONAD threshold value. During operation, the control system (100) decreases the attenuation of background noise levels for weak RF signals.

Speech-operated noise attenuation device (SONAD) control system method

A method of actuating a plurality of power amplifier devices in an Class D audio switching amplifier (100) using non-overlapping edge drive signals for preventing substantially high current spikes during switching transitions. The method includes actuating and deactuating power amplifier devices within a first complementary power switching device (117) and actuating and deactuating a second complementary power switching device (119) using a plurality of drive signals generated by a non-overlapping driver (107). The method provides that the first complementary power switching device (117) and the second complementary power switching device (119) are switched ON and OFF in a predetermined sequence such that more than one power amplifier device within each complementary power switching pair is prevented from being simultaneously activated. This prevents high current spiking and subsequently high current drain during a switching transition for conserving battery life when used with portable equipment.

Method of driving a class D audio power amplifier using non-overlapping

An audio amplifier clipping avoidance apparatus (140) identifies signal segments of an audio signal that can have an amplitude peak greater than a particular amplifier clip avoidance threshold (530). A scaling factor is determined for each signal segment based on the particular threshold (540). Signal segments are scaled with corresponding scaling factors to produce a modified audio signal having no signal segments with an amplitude peak greater than the particular threshold (560).

Audio amplifier clipping avoidance method and apparatus

A receiver automatic gain control (AGC) circuit includes a first adjustable gain control amplifier (158) which is responsive to a gain control signal (156). The AGC circuit further includes a second adjustable gain control amplifier (114) and a control circuit (116) which receives the gain control signal (156) and provides a modified gain control signal or VCNTRL (152) to the second adjustable control amplifier (114). The control circuit (116) also limits the amount of gain control applied to adjustable gain control amplifiers (114 and 118) when the gain control signal (156) reaches a certain predetermined level. This provides for all further gain reduction to occur at the first adjustable gain control amplifier (158) and thereby reduce the chances for distortion under high input signal conditions.

Zero intermediate frequency receiver having an automatic gain control

An amplifier (1) used with a pulse width modulated signal which improves the efficiency of a low level input signal comprises two or more switching devices (7,9) with common source/drain or emitter/collector connections. The gates or the bases of the devices are independently driven to optimize the efficiency of the various Rds (on) resistance values of the transistors (61, 63, 65, 89, 91, 93) used in the devices. The amplifier is operated so that during the highest output levels, select switching devices (61, 63, 65) are utilized to reduce in series resistance with the load (13). As output power decreases, devices (89, 91, 93) with higher Rds (on) resistance values are activated by a control signal which greatly improves DC to DC conversion efficiency with improved output voltage resolution, dynamic range and reduced electromagnetic interference potential.

Means and method of enhancing signal resolution and dynamic range

A voltage multiplier rectifier filter circuit comprising capacitors C3 and C4 and diodes D1 and D3 multiples, rectifies and filters the voltage at an input terminal (T1) of the switch. A diode (D2) is connected to the output of the multiplier-rectifier-filter circuit to provide a lesser bias voltage in the absence of a signal at the input terminal (T1). Four transistors (Q1-Q4) switch this bias voltage ON and OFF to the gates of four GaAs transistors (S1-S4). The GaAs transistors selectively couple signals between the input and output signal terminals (T1-T4) of the switch.

Gallium arsenide antenna switch having voltage multiplier bias circuit

An electronic switch uses GaAs transistors to switch signals that have peak-to-peak voltage swings that exceed the breakdown voltage of the transistors. A two port impedance transformer (Z1) has a high input impedance and a low output impedance to transform a high voltage input signal (at T1) to a corresponding output signal having lower voltage, but higher current. This transformed signal is coupled to the second port of a three port impedance transformer (Z2) through a first GaAs transistor switch (Q1). A half wave rectifier circuit (D1, R7, R8 and C3) generates a negative DC voltage from the input signal (at T1), thereby eliminating the requirement for a separate bias voltage supply. A bipolar transistor switch selectively couples this negative bias voltage to the gate of the first GaAs transistor (Q1). The second port of the three port impedance transformer (Z2) has a lower impedance than either the first or third ports. A second GaAs transistor switch (Q2) is coupled between the third port of the three port impedance transformer (Z2) and ground, and a third GaAs transistor switch (Q3) couples the third port to a output terminal (T6) of the switch. The first port of the three port impedance transformer (Z2) is coupled to an input/output terminal (T2) of the switch.

Gallium arsenide antenna switch

An RF signal is transformed (12 and 12') to increase its current component, while reducing its voltage component below the voltage that would damage a GaAs switching device (16 or 16'). The current and voltage transformation are selected so that the power of the RF signal remains substantially constant. Subsequent to the GaAs switching device, the signal is converted (24 and 24') to increase the voltage component while decreasing its current component to substantially recreate the original RF signal.

A single input, differential output amplifier (50) includes two Gallium Arsenide field effect transistors: one arranged to form a common gate amplifier (55) to provide a non-inventing output (60), and the other arranged to form a common source (65) amplifier to provide an inverting output (61). The input of each FET is connected to receive an input signal simultaneously thereby minimizing phase delay in the differential output signals. In another aspect of the invention, the non-inverting stage (55) is incorporated into the biasing network for the inverting ampllifier (65).

Signal input to differential output amplifier

A variable capacitance circuit includes a varactor having an anode side and a cathode side. A first variable bias voltage is applied to one of the sides and one of a plurality of voltages is applied as a second bias voltage to the other side for controlling the capacitance of the varactor. A voltage multiplier circuit connected to a voltage divider network is used for supplying the plurality of voltages. A decoder is responsive to input signals for selecting and applying one of the multiple voltage outputs. The variable capacitance circuit is used in a voltage controlled oscillator of a frequency synthesizer for providing extended frequency range.

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Miami, FL, United States of America

Enrique Ferrer