Optimum Semiconductor Technologies Inc.

Enrique A Barria

Lei Wang

Mayan Moudgill

Gary J Nacer

Paul Hurtley

A Joseph Hoane

Aaron G Milbury

A processor includes a translation lookaside buffer (TLB) comprising a plurality of ways, wherein each way is associated with a respective page size, and a processing core, communicatively coupled to the TLB, to execute an instruction associated with a virtual memory page, identify a first way of the plurality of ways, wherein the first way is associated with a first page size, determine an index value using the virtual memory page and the first page size for the first way, determine, using the index value, a first TLB entry of the first way, and translate, using a memory address translation stored in the first TLB entry, the first virtual memory page to a first physical memory page.

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Bronxville, NY, United States of America

Enrique A Barria