Sgs-thomson Microelectronics S.r.l.

Stmicroelectronics S.r.l.

Enrico M Ravanelli

Flavio Francesco Villa

Giulio Ricotti

Pietro Erratico

Giorgio Pedrazzini

Pietro Consiglio

Massimo Pozzoni

Antonio Andreini

Francesco Pulvirenti

Fabrizio Martignoni

Luca Fontanella

Lucia Zullino

The present invention relates to a circuit device for protection against electrostatic discharge, and being immune to the latch-up phenomenon. The circuit device is of the integrated type in a portion of a semiconductor integrated circuit. The device includes an active limiting element and a resistor connected in series between a terminal of the active element connected to an input/output pin of the integrated circuit, and a terminal of a circuit to be protected. The active element is a bipolar transistor having a base terminal and an emitter-acting collector terminal connected together. The distributed resistor is formed in an emitter-acting collector region of the transistor which is diffused and elongated at the surface inside a base pocket of the transistor.

Circuit device for protection against electrostatic discharge, immune to the latch-up phenomenon

A suppression method is applied to an integrated circuit formed on a substrate of p-type material having at least one region of n-type material with junction isolation, a first electrical contact on the frontal surface of the substrate, a second electrical contact on the n-type region and a third electrical contact on the back of the substrate connected to a reference (ground) terminal of the integrated circuit. To avoid current in the substrate due to the conduction of parasitic bipolar transistors in certain operating conditions of the integrated circuit, the method provides for monitoring the potential of the second contact to detect if this potential departs from the (ground) potential of the reference terminal by an amount greater than a predetermined threshold value. If this occurs the first contact is taken to the potential of the second contact, otherwise they are held at the (ground) potential of the reference terminal. A device and an integrated circuit which utilize the method are also described.

Method for suppressing parasitic effects in a junction-isolation integrated circuit

An electrostatic discharge protection circuit for integration into an integrated circuit device. The protection circuit includes at least one transistor having a first terminal connected to an input or output terminal of the integrated circuit device, a second terminal connected to a supply line for the integrated circuit device, and a control terminal connected to ground. In a preferred embodiment, the transistor is formed by a structure that includes a substrate of a first conductivity type, a first region of a second conductivity type, a second region of the first conductivity type, a third region of the first conductivity type, and a fourth region of the second conductivity type. The third region has greater conductivity than the substrate and the fourth region has greater conductivity than the first region. These regions are formed such that the first region extends from a surface of the substrate, the second region extends from the surface into a portion of the first region, and the third region has one portion buried beneath the first region and another portion extending to the surface. Additionally, the fourth region extends from the second region with a ring shape so as to form a bipolar junction with the second region in an area beneath a non-peripheral portion of the second region.

Device for protecting an integrated circuit against electrostatic

A protection circuit for a power supply line in a semiconductor device, comprising first and second field-effect transistors, both transistors having their respective drain terminals connected to the power supply line. The gate source terminals of the first transistor are connected to ground through first and second resistors, respectively. The gate and source terminals of the second transistor are connected to the source terminal of the first transistor and to ground, respectively.

Protection circuit for an electric supply line in a semiconductor

A protection circuit for a pulse type power supply line of an integrated circuit device. The protection circuit includes a switching circuit having a preset delay, and a first transistor that is connected between the pulse power supply line and ground. The gate terminal of the first transistor is coupled to ground through a first resistor, and to a second power supply line for a low DC voltage through the switching circuit. In a preferred embodiment, the switching circuit includes a second transistor that is connected between the gate terminal of the first transistor and ground. The gate terminal of the second transistor is coupled to the second power supply line through a current generator, and is also coupled to ground through a resistive element and a capacitive element that are connected in parallel.

Protection circuit for an electric pulse supply line in a semiconductor

Method and device for suppressing parasitic effects in a

The device has an SCR structure in a P surface zone of a silicon die. A P+ anode region for connection to an I/O terminal to be protected is formed in an N region, as well as an N+ contact region; an N+ cathode region is formed in another N region for connection to the earth of the integrated circuit. The striking potential of the SCR, that is, the intervention potential of the protection device, is determined by the reverse breakdown of the junction between the first N region and the P-body surface zone. This potential is influenced by an electrode which is disposed over the junction and is connected to the cathode constituting the gate of a cut-off N-channel MOS transistor. The concentrations are selected in a manner such that the P-channel MOS transistor defined by the P region, by the portion of the first region over which the electrode is disposed, and by the P-body, has a conduction threshold greater than the striking potential. The device can be integrated in a very small area and is very efficient in terms of both energy and response speed.

Electrostatic-discharge protection device and method for making the same

A circuit protects against electrostatic discharge and includes a transistor connected to the circuit to be protected. A semiconductor body of a first conductivity type serves as the collector. A first doped region of a second conductivity type is contained in the semiconductor body and serves as the base. A second doped region of the first conductivity type is contained in the first doped region and serves as the emitter. The first doped region includes a generally H-shaped doped region and a generally ring-shaped doped region forming an opening in which the second doped region serving as the emitter is received. The H-shaped doped region has a deeper junction surface than the junction surface of the ring-shaped doped region, and a dopant concentration that is less than the dopant concentration of the ring-shaped doped region. The H-shaped doped region achieves a low collector-to-base breakdown voltage and the ring-shaped doped region achieves a low snap-back voltage. A method for forming the transistor is also disclosed.

Electrostatic discharge protection circuit and transistor

A device for protecting an integrated circuit against electrostatic discharges, and adapted for connection between a terminal and a ground of the integrated circuit, which includes a first transistor (Q2) connected between that terminal and ground by its emitter terminal and collector terminal, respectively, and a second transistor (Q1) which has its base terminal connected to the base terminal of the first transistor. The emitter and collector terminals of the second transistor (Q2) are connected to the collector of the first transistor (Q1).

Device for the protection of an integrated circuit against electrostatic

Device for limiting the working voltage for mechanical switches in telephony includes terminals for connection to a telephone line, a connection and power supply branch for a control circuit extending from a first terminal, the branch having a first switch, the cathode terminal of a first Zener diode and the source terminal of a first MOSFET transistor being connected to the output terminal of the first switch, the gate terminal of the first MOSFET transistor being connected, through the anode terminal of the Zener diode, to the first terminal. The current absorbed by the device may be adjusted.

Device for limiting the working voltage for mechanical switches in

The breakdown characteristics of a lateral transistor integrated in an epitaxial layer of a first type of conductivity grown on a substrate of an opposite type of conductivity and comprising a drain region formed in said epitaxial layer, are markedly improved without recurring to critical adjustments of physical parameters of the integrated structure by forming a buried region having the same type of conductivity of the substrate and a slightly higher level of doping at the interface between the epitaxial layer and the substrate in a zone laying beneath the drain region of the transistor.

Method for fabricating a fully depleted lateral transistor

Fully depleted lateral transistor

An integrated device includes isolating regions of a first type of conductivity, each surrounding an epitaxial pocket of an opposite type of conductivity, and housing drain and source regions, and covered with an oxide layer housing gate regions and over which extend the source, drain and gate connections. For linearizing potential distribution at the epitaxial pocket--isolating region junction and close to the source regions beneath the connections, these regions are provided with a double chain of condensers embedded in the oxide layer and the terminal elements and the intermediate element of which are biased to predetermined potentials.

Method of making junction-isolated high voltage MOS integrated device

Device for limiting the working voltage mechanical switches in telephony

An integrated device includes isolating regions of a first type of conductivity, each surrounding an epitaxial pocket of an opposite type of conductivity, and housing drain and source regions, and covered with an oxide layer housing gate regions and over which extend the source, drain and gate connections. For linearizing potential distribution at the epitaxial pocket-isolating region junction and close to the source regions beneath the connections, these regions are provided with a double chain of condensers embedded in the oxide layer and the terminal elements and the intermediate element of which are biased to predetermined potentials.

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Monza, Italy

Enrico M Ravanelli