Stmicroelectronics International N.v.

St-ericsson Sa

Ennio Salemi

Gilles Ries

Sana Ben Alaya

A memory management system for managing a memory and includes a multi-stage memory management unit including control circuitry and cache memory. The cache memory may have a respective translation look-aside buffer for each stage of the multi-stage memory management unit. The control circuitry may be configured to generate a blank data request including a virtual address and information that specifies that data is not to be read from the memory, perform address translations based on the generated blank data request in multiple stages until a physical address is obtained, and discard the blank data request.

Pre-fetch in a multi-stage memory management system

A memory management unit may send page table walk requests to a page table descriptor in a main memory system and receive address translation information, with the page table walk requests including information that specifies an amount of further address translation information, and receive the further address translation information. The cache unit may intercept the page table walk requests, and modify content of the intercepted page table walk requests so the information that specifies the amount of further address translation information is extended from a first amount to a second amount greater than the first amount. The cache unit may store the second amount of further address translation information for use with data requests that are subsequent to a current data request, and provide the address translation information based upon an intercepted page table walk request being associated with address translation information already stored in the cache unit.

Enhanced pre-fetch in a memory management system

The method of transferring data between a first and a second set of elements via a switch that includes a set of paths each associated with a weighting coefficient representing a data stream for each path. The method includes a credit flow control between the first set of elements and the switch and a credit flow control between the switch and the second set of elements. An available credit coefficient is computed for each element of the first set on the basis of a credit allocated by each element of the second set and of the weighting coefficient of each path.

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Grenoble, France

Ennio Salemi