Marvell International Limited

Goke US Research Laboratory

Marvellworld Trade Ltd.

Stmicroelectronics Gmbh

University of California

Stmicroelectronics S.r.l.

Engling Yeo

Panu Chaichanavong

Gregory Burd

Zining Wu

Nedeljko Varnica

Shaohua Yang

Jun Xu

Henri Sutioso

Eugene Pan

Xinhai Kang

Steven Schauer

Chandra Varanasi

Ko-Chung Tseng

Farshid Rafiee Rad

Manoj Kumar Yadav

Yuan-Mao Chang

William G Bliss

Jie Chen

Yu Liao

Stefano Valle

Massimiliano Siti

Richard Wesel

Andres I Vila Casado

Wen-Yen Weng

Neelmani Kumar

Nicola Moschini

Haoting Luo

A method and apparatus for improved data recovery in data storage systems is described. When errors occur while retrieving a plurality of codewords from a plurality of storage devices, a long vector may be formed from the plurality of codewords and decoded by a special, long parity check matrix to re-create data stored on the plurality of storage devices when normal decoding efforts fail.

Method and apparatus for improved data recovery in data storage systems

A system, method and apparatus for compressing and decompressing data. A host processor and host memory are coupled to a block I/O device. The host processor issues compress and decompress commands to the block I/O device in accordance with a high-speed data storage and retrieval protocol. The block I/O device compresses/decompresses the data specified in the compress/decompress command, thus relieving the host processor of performing the compression/decompression and freeing the host processor for other tasks.

Method and apparatus for data compression and decompression using a standardized data storage and retrieval protocol

A system, method and apparatus for encoding and decoding data. A host processor and host memory are coupled to a block I/O device. The host processor issues encode and decode commands to the block I/O device in accordance with a high-speed data storage and retrieval protocol. The block I/O device encodes the data specified in the encode command, thus relieving the host processor of performing the encoding/decoding and freeing the host processor for other tasks.

Method and apparatus for data encoding and decoding using a standardized data storage and retrieval protocol

A method and apparatus is described for assigning columns of an LDPC H matrix to a plurality of decoding logics for efficient decoding of codewords. The rows of the LDPC H matrix are evaluated in a number of different orderings, and for each row in each ordering, a number of columns containing non-zero circulants are determined that cannot be evenly distributed to a plurality of decoding logics. As each row is evaluated, one or more columns of the LDPC H matrix are assigned to temporary bins for storage. After the LDPC H matrix has been evaluated a plurality of times, the arrangement that resulted in the fewest number of 'mismatched' columns is selected, and the columns of the LDPC H matrix that were assigned to the temporary storage bins for that particular row arrangement is used to assign the columns in the bins to the plurality of decoding logics.

Method and apparatus for efficient data decoding

A system, method and apparatus for encrypting data. A host processor and host memory are coupled to a block I/O device. The host processor issues encryption and decryption commands to the block I/O device in accordance with a high-speed data storage and retrieval protocol. The block I/O device performs encryption on data specified in the encryption command, thus relieving the host processor of performing the encryption and freeing the host processor for other tasks.

Method and apparatus for data encryption using a standardized data storage and retrieval protocol

A method and apparatus for efficient data decoding is described. Data is encoded by an LDPC encoder using a G matrix. An LDPC decoder uses a modified H matrix to decode encoded blocks of data, the modified H matrix having at least two columns of its circulants swapped with each other. The encoded blocks of data are stored, decoded and reconstructed in an order that considers the circulants in the columns that have been swapped.

Look-ahead LDPC decoder. In an exemplary embodiment, a method includes generating a message (QA) to a first check node, the QA message is generated from a result (RA) from the first check node, and generating a message (QB) to a second check node, the QB message is generated from the result (RA) and is transmitted to avoid decoder stall. The method also includes receiving a result (R'A) from the first check node, computing a difference (R&#x2033;A) between the result (R&#x2032;A) and the result (RA), and receiving a result (R&#x2032;B) from the second check node. The method also includes computing a bit value P(B) using the difference (R&#x2033;A) and the result (R&#x2032;B).

Look-ahead LDPC decoder

There is provided, in accordance with an embodiment, a method of decoding codewords in conjunction with a low-density parity-check (LDPC) code that defines variable nodes and check nodes, the method comprising receiving a codeword over a data channel; evaluating quality of the data channel; and iteratively updating values of the variable nodes to decode the codeword; wherein the values of the variable nodes are updated at different levels of numeric precision depending on the evaluated quality of the data channel.

Method and apparatus for reducing idle cycles during LDPC decoding

Methods and systems are disclosed for decoding codewords, wherein codewords comprise at least one circulant and are stored in a first dimension of a matrix, and wherein each circulant in a codeword is associated with a location in a second dimension in the matrix. The method includes determining whether a first location in a second dimension of a first circulant of a first codeword corresponds to a second location in the second dimension of a second circulant of a second codeword. The method includes, in response to determining that the first location does not correspond to the second location, decoding the first and second circulant with a first decoding process. The method includes, in response to determining that the first location corresponds to the second location, decoding the first and second circulant with a second decoding process.

Methods and systems for parallelizing high throughput iterative decoders

Method and apparatus for power conservation in LDPC decoding

Disclosed herein are systems and methods for a signed-magnitude adder based on one's complement logic, where the adder offers enhancements in both speed and chip area consumption. The one's complement based adder includes circuitry for converting operands from their signed-magnitude representations to their one's complement representations, circuitry for adding operands in their one's complement representations, and circuitry for converting the resulting sum into a signed-magnitude format.

Systems and methods for a signed magnitude adder in one's complement logic

Systems, methods, and other embodiments associated with decoder based data recovery are described. According to one embodiment, an apparatus includes a decoder configured to decode codewords and decoder firmware configured to control one or more decoding parameters of the decoder. The decoder includes a recovery unit configured to store recovery instructions. The decoder is further configured to execute the stored recovery instructions without interaction with the decoder firmware when the decoding fails.

Decoder based data recovery

The present disclosure includes systems and methods for acquiring a first set of information for a plurality of low density parity check (LDPC)-encoded data symbols, acquiring a second set of information for the plurality of LDPC-encoded data symbols, and selecting a window including a subset of the plurality of LDPC-encoded data symbols. The present disclosure includes acquiring a decoder schedule having information for controlling the decoder, wherein the information in the decoder schedule includes decoding instructions based on a configuration of at least one of the first set of information and the second set of information. The present disclosure further includes determining a likelihood of an error in the window using the decoding instructions in the decoder schedule, and updating the second set of information for selected data symbols of the subset based on the likelihood of an error in the window.

Methods and systems for reconfigurable LDPC decoders

A group of numbers from which the smallest and second-smallest are to be selected are compared in a cascaded tree. Each comparison stage will select the smallest number from two numbers output by the previous stage, into which four numbers are input. The second-smallest number is one of the other three inputs to the previous stage and, as before, all bits of the second-smallest number will not be known until the smallest number is determined. However, because at each stage of the determination, the next stage is reached because the bit values being examined are the same, those bit values of the second-smallest number (and indeed of the smallest number) are known ahead of the final determination of the smallest number. Accordingly, one can begin to output bits of the second-smallest number (as well as of the smallest number) even before that final determination.

Bitwise comparator for selecting two smallest numbers from a set of numbers

Systems, methods, and other embodiments associated with iterative decoders are described. According to one embodiment, an apparatus includes a set of decoders that are configured to receive data to be decoded. The apparatus may also include a controller configured to separately control each decoder to initiate a decoding sequence based on an occurrence of a transition point. The transition point is a global transition that occurs iteratively for the set of decoders and is based on iterations in a decoding sequence.

Growing community of inventors

San Jose, CA, United States of America

Engling Yeo