Intel Corporation

Cornell Research Foundation Inc.

Engin Ipek

Daehyun Kim

Mikhail Smelyanskiy

Anthony Nguyen

Victor W Lee

Victor Y Lee

José F Martínez

Meyrem Kirman

Nevin Kirman

Methods and apparatus to provide virtualized vector processing are described. In one embodiment, one or more operations corresponding to a virtual vector request are distributed to one or more processor cores for execution.

Virtual vector processing

Methods and apparatus to provide virtualized vector processing are disclosed. In one embodiment, a processor includes a decode unit to decode a first instruction into a decoded first instruction and a second instruction into a decoded second instruction, and an execution unit to: execute the decoded first instruction to cause allocation of a first portion of one or more operations corresponding to a virtual vector request to a first processor core, and generation of a first signal corresponding to a second portion of the one or more operations to cause allocation of the second portion to a second processor core, and execute the decoded second instruction to cause a first computational result corresponding to the first portion of the one or more operations and a second computational result corresponding to the second portion of the one or more operations to be aggregated and stored to a memory location.

A reconfigurable multiprocessor system including a number of processing units and components enabling executing sequential code collectively at processing units and enabling changing the architectural configuration of the processing units.

Systems and methods for reconfiguring on-chip multiprocessors

Growing community of inventors

Ithaca, NY, United States of America

Engin Ipek