University of Rochester

Samsung Electronics Co., Ltd.

Huawei Technologies Co., Limited

Engin Ipek

Eby G Friedman

Mohammad Kazemi

Ravi Patel

Isaac Richter

Xiaochen Guo

Kamil Pas

Ji Liu

Mahdi Nazm Bojnordi

Borna Josip Obradovic

Jorge A Kittl

Titash Rakshit

Ryan M Hatcher

Shihai Xiao

Florian Longnos

Arun S Jagatheesan

Ben Feinberg

Shibo Wang

A method of storing a sparse weight matrix for a trained artificial neural network in a circuit including a series of clusters. The method includes partitioning the sparse weight matrix into at least one first sub-block and at least one second sub-block. The first sub-block includes only zero-value weights and the second sub-block includes non-zero value weights. The method also includes assigning the non-zero value weights in the at least one second sub-block to at least one cluster of the series of clusters of the circuit. The circuit is configured to perform matrix-vector-multiplication (MVM) between the non-zero value weights of the at least one second sub-block and an input vector during an inference process utilizing the artificial neural network. The sub-blocks containing all zero elements are power gated, thereby reducing overall energy consumption for inference.

Method of enabling sparse neural networks on memresistive accelerators

A method of controlling a trajectory of a perpendicular magnetization switching of a ferromagnetic layer using spin-orbit torques in the absence of any external magnetic field includes: injecting a charge current Jthrough a heavy-metal thin film disposed adjacent to a ferromagnetic layer to produce spin torques which drive a magnetization M out of an equilibrium state towards an in-plane of a nanomagnet; turning the charge current Joff after tseconds, where an effective field experienced by the magnetization of the ferromagnetic layer His significantly dominated by and in-plane anisotropy H, and where M passes a hard axis by precessing around the H; and passing the hard axis, where His dominated by a perpendicular-to-the-plane anisotropy H, and where M is pulled towards the new equilibrium state by precessing and damping around H, completing a magnetization switching.

Switching of perpendicularly magnetized nanomagnets with spin-orbit torques in the absence of external magnetic fields

A memory device includes a storage unit array and a controller. The storage unit array contains storage units arranged in M rows and N columns and has M word lines and N bit line pairs. Each of the N bit line pairs includes a bit line and a source line. In operation, after obtaining Q rows of data that are to be written into Q rows of storage units in the storage unit array, the controller writes a first value into each of storage units in a column j in P columns of storage units. The controller then determines to-be-written rows in the Q rows of data, and writes in parallel a second value into each of storage units of the to-be-written rows in the storage units in the column j.

Memory device and method for writing data

A base element for switching a magnetization state of a nanomagnet includes a heavy-metal nanostrip having a surface. A ferromagnetic nanomagnet is disposed adjacent to the surface. The ferromagnetic nanomagnet includes a shape having a long axis and a short axis. The ferromagnetic nanomagnet has both a perpendicular-to-the-plane anisotropy Hand an in-plane anisotropy Hand the ferromagnetic nanomagnet has a first magnetization equilibrium state and a second magnetization equilibrium state. The first magnetization equilibrium state or the second magnetization equilibrium state is settable by a flow of electrical charge through the heavy-metal nanostrip. A direction of flow of the electrical charge through the heavy-metal nanostrip includes an angle &#x3be; with respect to the short axis of the nanomagnet.

An energy efficient rapid single flux quantum (ERSFQ) logic register wheel includes a circular shift register having a plurality of destructive read out (DRO) cells. Each entry of the circular shift register includes a data block, a tag, and a valid bit. A compare and control logic is coupled to the circular shift register to compare a source specifier or a destination register specifier against a register tag stored in the wheel following each cycle of the register wheel. At least one or more read ports and at least one or more write ports are coupled to the circular shift register to write to or to read from a different entry each in the register wheel following each cycle of the register wheel. A RSFQ clearable FIFO with flushing and a crosspoint memory topology for integrating MRAM devices with ERSFQ circuits are also described.

Superconducting system architecture for high-performance energy-efficient cryogenic computing

A base element for switching a magnetization state of a nanomagnet includes a heavy-metal strip having a surface. A ferromagnetic nanomagnet is disposed adjacent to the surface. The ferromagnetic nanomagnet has a first magnetization equilibrium state and a second magnetization equilibrium state. The first magnetization equilibrium state or the second magnetization equilibrium state is settable in an absence of an external magnetic field by a flow of electrical charge through the heavy-metal strip. A method for switching a magnetization state of a nanomagnet is also described.

Presented is a method and apparatus for solving. The method includes receiving, by a resistive memory array, a first data, the resistive memory array comprising a plurality of cells, wherein the receiving comprises setting a plurality of resistances on the plurality of cells, wherein each of the plurality of resistances are based on the first data. The method further includes receiving, by the resistive memory array, a second data, wherein the receiving comprises applying at least one of a current and a voltage based on the second data on the plurality of cells. The method still further includes determining, by the resistive memory array, an initial unknown value, the initial value based on the first data and the second data.

Resistive memory accelerator

A method includes receiving, by a resistive memory array, a first data, the resistive memory array comprising a plurality of cells, wherein the receiving comprises setting a plurality of resistances on the plurality of cells, wherein each of the plurality of resistances are based on the first data. The method further includes receiving, by the resistive memory array, a second data, wherein the receiving comprises applying at least one of a current and a voltage based on the second data on the plurality of cells. The method still further includes determining, by the resistive memory array, an initial unknown value, the initial value based on the first data and the second data.

One embodiment includes a programmable memory controller. The programmable memory controller includes a request processor that comprises a first domain-specific instruction set architecture (ISA) for accelerating common requests. A transaction processor comprises a second domain-specific ISA for accelerating transaction processing tasks. A dedicated command logic module inspects each memory command to a memory device and stalls particular commands for meeting timing constraints for application specific control of the memory device.

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Rochester, NY, United States of America

Engin Ipek