Altera Corporation

Intel Corporation

Eng Ling Ho

Sean R Atsatt

Chiew Siang Wong

Chin Hai Ang

Ee Mei Ooi

Rob Pelt

Michael David Hutton

Dana How

Ping-Chen Liu

James Loran Ball

Jeffrey Christopher Chromczak

Zunhang Yu Kasnavi

Siaw Chen Lee

Shen Shen Lee

Kok Wah Khor

Chai Ling Chee

Methods and systems for configuring a programmable logic device include receiving configuration data at an input of a first sector of the programmable logic device and dynamically routing the configuration data through the first sector to a second sector of the programmable device by selecting a first routing path out of the first sector or a second routing path out of the first sector.

Configuration of a programmable device

One embodiment relates to a method of controlling supply voltage regulation within an integrated circuit. An external interrupt is sent from an external interaction processing layer to a processor in the integrated circuit. Off-die instructions are generated by the external interaction processing layer and sent to the processor. The off-die instructions are executed by the processor to test and adjust supply voltage regulation within the integrated circuit on a sector-by-sector basis. Another embodiment relates to a method of controlling a supply voltage regulator for a sector of an integrated circuit. Commands are sent by a processor and translated by a sector manager to bits. The bits are loaded into registers so as to set the regulator control circuit to the testing mode send a supply voltage to an analog-to-digital converter. Other embodiments and features are also disclosed.

Apparatus and method of voltage regulation control for integrated circuit

A system may include a host processor and a coprocessor for accelerating tasks received from the host processor. The coprocessor may include programmable circuitry organized into logic sectors. Each logic sector may have a dedicated local sector manager (LSM). The LSMs may be controlled by a secure device manager (SDM). The SDM may be coupled to data unloading circuitry for unloading configuration data from the coprocessor off onto the host processor. The unloading circuitry may include a circular first-in first-out (FIFO) buffer circuit that can be divided into multiple partitions to store configuration data from the various LSMs. The FIFO buffer circuit may be configured as an input FIFO in a configuration (loading) mode or as an output FIFO in a data unloading mode.

Methods and apparatus for unloading data from a configurable integrated circuit

An integrated circuit may include user storage circuits and scan storage circuits. The scan storage circuits may store data from the user storage circuits and provide the data to a user interface during a read-back operation. The user storage circuits may store data from the scan storage circuits, which the scan storage circuits may have received from the user interface during a write-back operation. The scan storage circuits may be arranged in a scan chain and controlled by a local control circuit. The integrated circuit may include multiple local control circuits that each control a sector of the integrated circuit. The local control circuits may communicate with a global control circuit over a communication network, and the global control circuit may communicate with the user interface.

Techniques for using scan storage circuits

An apparatus to test a parametric structure utilizing a logical sensing technique is provided. The apparatus includes a device under test (DUT) and tester hardware. The DUT includes a parametric structure that receives a logic signal and transfers the logic signal through the parametric structure to a power pin that is coupled to the parametric structure. The DUT also includes a DFT circuitry that controls a pathway connecting the parametric structure and the power pin. The DFT circuitry gates the logic signal propagation from the parametric structure to the power pin. The tester hardware includes a channel to transfer or receive a logic signal and a power pathway to transfer power to the DUT. The tester hardware also includes a switch to multiplex the power pathway or the channel connections to the power pin.

Apparatus and a method to test a parametric structure utilizing logical sensing

Integrated circuits such as programmable logic device integrated circuits have configuration random-access memory elements. The configuration random-access memory elements are tested to determine whether any of the elements have resistive bridging faults at their outputs. During testing, a pattern of test configuration data is loaded into the configuration random-access memory elements. The programmable logic device is placed in user mode to clear programmable logic registers on the device. The configuration random-access memory elements are sensitized to the presence of resistive bridging faults by performing read operations. After sensitizing the configuration random-access memory elements, a tester applies test vectors to the programmable logic of the programmable logic device. As the test vectors are applied, the tester observes whether the programmable logic of the device is performing properly or has been affected by the presence of a resistive bridging fault.

Methods for detecting resistive bridging faults at configuration random-access memory output nodes

Methods and apparatus for testing programmable integrated circuits are provided. Programmable integrated circuits include programmable elements that are loaded with configuration data to program programmable logic to perform a custom logic function. The programmable integrated circuits receive test configuration data from a tester to program the programmable logic into a test configuration. After the programmable integrated circuit has been placed into the test configuration by loading the test configuration data, test vectors are applied to the programmable integrated circuit to evaluate its performance. Test configuration data loading circuits are used in the programmable integrated circuits to control how the test configuration data is loaded into the programmable elements. When the adjustable circuits are placed in a low bandwidth configuration, relatively few input lines are used to load the test configuration data. When the adjustable circuits are placed in a high bandwidth configuration, test data can be loaded quickly.

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Simpang Ampat, Malaysia

Eng Ling Ho