Globalfoundries Singapore Pte. Ltd.

Globalfoundries U.S. Inc.

National University of Singapore

Globalfounders Singapore Pte. Ltd.

Eng Huat Toh

Shyue Seng Tan

Kiok Boone Elgin Quek

Elgin Kiok Quek

Elgin Kiok Boone Quek

Desmond Jia Jun Loy

Lanxiang Wang

Ping Zheng

Yongshun Sun

Xinshu Cai

Chung Foong Tan

Jae Gon Lee

Bin Liu

Xuan Anh Tran

Yuan Sun

Ruchil Kumar Jain

Danny Pak-Chum Shum

Vinayak Bharat Naik

Juan Boon Tan

Sanford Chu

Ming Zhu

Kangho Lee

Kazutaka Yamane

Shyue Seng (Jason) Tan

Khee Yong Lim

Pinghui Li

Hemant M Dixit

Yiang Aun Nga

Chenchen Jacob Wang

Samarth Agarwal

Wei Chang

Yinjie Ding

Ying Keung Leung

Shiang Yang Ong

Danny Shum

Chunshan Yin

Jianxun Sun

Xinfu Liu

Shyue Seng Jason Tan

Sriram Balasubramanian

Yanzhe Tang

Francesco Gramuglia

Eric Linardy

Su Yi Susan Yeow

Cancan Wu

Dimitri Houssameddine

Curtis Chun-I Hsieh

Steven R Soss

Wei Ling Chang

Jeoung Mo Koo

Lup San Leong

Jack Tim Wong

Benfu Lin

Siow Lee Chwa

Lakshmi Kanta Bera

Kin Wai Tang

Yoke Leng Lim

Tu Pei Chen

Dexter Xueming Tan

Michael Nicolas Albert Tran

Yee Chia Yeo

Kien Seen Daniel Chong

Xueming Dexter Tan

Meng Yew Seah

Jing Hua Michelle Tng

Kian Hui Goh

Kian Ming Ng

George Mulfinger

Thanh Hoa Phung

Guoquan Teo

Zar Lwin Zin

Ming Tsang Tsai

Anson Heryanto

Jacob Chenchen Wang

A ferroelectric transistor (FeFET) memory device includes a metal gate, a gate dielectric layer adjacent to the metal gate, a semiconductor channel layer adjacent to the gate dielectric layer, a metal drain electrode, and a metal source electrode recessed into the semiconductor channel layer. The metal gate may be oriented above or below the metal source and drain electrodes with respect to a semiconductor substrate.

Fe-FET structure with buried electrode

The disclosed subject matter relates generally to structures for use in memory devices. More particularly, the present disclosure relates to three terminal resistive random-access (ReRAM) memory structures having source, drain, and control electrodes. The present disclosure provides a memory structure including a source electrode, a drain electrode, a control electrode laterally between the source electrode and the drain electrode, a hole generating layer above the control electrode, a dielectric channel layer above the hole generating layer, the dielectric channel layer contacts the source electrode and the drain electrode, a first spacer layer on a first side of the control electrode, and a second spacer layer on a second side of the control electrode. The first spacer layer and the second spacer layer isolate the source electrode and the drain electrode from the control electrode and the hole generating layer.

Structures for three-terminal memory cells

Structures for a non-volatile memory and methods of forming such structures. A gate electrode and a gate dielectric layer are formed over an active region with the gate dielectric layer between the gate electrode and the active region. A first doped region is formed in the active region, a second doped region is formed in the active region, and a source line is coupled to the second doped region. The first doped region is positioned in the active region at least in part beneath the gate dielectric layer, and the second doped region is positioned in the active region adjacent to the first doped region. The first doped region has a first conductivity type, and the second doped region has a second conductivity type opposite to the first conductivity type.

Non-volatile memory elements with one-time or multiple-time programmability

The disclosed subject matter relates generally to structures, memory devices and a method of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices having a spacer element on a side of the electrode. The present disclosure provides a memory device including a first electrode having a side, the side has upper and lower portions, a spacer element on the lower portion of the side of the first electrode, a resistive layer on the upper portion of the side of the first electrode, and a second electrode laterally adjacent to the side of the first electrode. The second electrode has a top surface, in which the top surface has a concave profile.

Memory devices and methods of making the same

Structures including a photodetector, such as a single-photon avalanche diode, and related methods. The structure comprises a semiconductor layer having a device region and a top surface, and a photodetector including a first well in the device region and a second well. The first well is disposed between the second well and the top surface. The structure further comprises a deep trench isolation region that extends from the top surface into the semiconductor layer. The deep trench isolation region surrounds a perimeter of the device region, and the deep trench isolation region comprises a dielectric material. The structure further comprises a contact including a conductor layer that extends from the top surface of the semiconductor layer to the second well. The contact has a first discrete position about the perimeter of the device region.

Structures including a photodetector and multiple cathode contacts

Structures for a photodetector and methods of forming a structure for a photodetector. The structure includes a semiconductor layer having a p-n junction and a deep trench isolation region extending through the semiconductor layer. The deep trench isolation region includes first layers and second layers that alternate with the first layers to define a Bragg mirror. The first layers contain a first material having a first refractive index, and the second layers contain a second material having a second refractive index that is greater than the first refractive index.

Photodetectors with a deep trench isolation region that includes a bragg mirror

The present disclosure generally relates to semiconductor devices for use in optoelectronic/photonic applications and integrated circuit (IC) chips. More particularly, the present disclosure relates to devices containing photodiodes such as avalanche photodiodes (APDs) and single photon avalanche diodes (SPADs). The present disclosure may provide a device including a substrate, a first well of a first conductivity type in the substrate, a second well of a second conductivity type in the substrate, and a buried layer of the second conductivity type in the substrate. The buried layer may be below the first well and the second well. The buried layer may have a first section and a second section, in which the first section has a larger thickness than the second section.

Optoelectronic device including photodiode having buried layer with different thicknesses

A memory device and method of making the same is provided. The memory device includes a first electrode, an oxygen scavenging layer on the first electrode, a hard mask on the oxygen scavenging layer, and a second electrode on the hard mask. A switching layer is arranged on a portion of the oxygen scavenging layer, and the switching layer is conformal to a side surface of the hard mask.

Non-volatile memory device with filament confinement

The disclosed subject matter relates generally to structures, memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices having two resistive layers and a conductive layer arranged between two electrodes. The present disclosure provides a memory device including a first electrode above an interlayer dielectric region, a second electrode above the interlayer dielectric region, the second electrode is laterally adjacent to the first electrode, a conductive layer between the first electrode and the second electrode, in which the conductive layer is electrically isolated, a first resistive layer between the first electrode and the conductive layer, and a second resistive layer between the second electrode and the conductive layer.

Lateral multi-bit memory devices and methods of making the same

Structures for a single-photon avalanche diode and methods of forming a structure for a single-photon avalanche diode. The structure includes a semiconductor layer having a first well and a second well defining a p-n junction with the first well, and an interlayer dielectric layer on the semiconductor layer. A deep trench isolation region includes a conductor layer and a dielectric liner. The conductor layer penetrates through the semiconductor layer and the interlayer dielectric layer. The conductor layer has a first end, a second end, and a sidewall that connects the first end to the second end. The dielectric liner is arranged to surround the sidewall of the conductor layer. A metal feature is connected to the first end of the conductor layer.

Single-photon avalanche diodes with deep trench isolation

Structures for an electronic fuse and methods of forming an electronic fuse. The structure includes a first terminal, a second terminal, and a fuse link extending from the first terminal to the second terminal. The structure further includes a silicide layer having a first portion included in the fuse link and a second portion included in the first terminal and the second terminal. The first portion of the silicide layer has a first thickness, the second portion of the silicide layer has a second thickness, and the first thickness is less than the second thickness.

Electronic fuses with a silicide layer having multiple thicknesses

The present disclosure relates to semiconductor structures and, more particularly, to temperature sensors with programmable magnetic tunnel junction structures and methods of manufacture. A structure includes a resistor material connected in series with a programmable magnetic tunnel junction structure in a Wheatstone bridge configuration.

Programmable magnetic tunnel junction

The embodiments herein relate to semiconductor memory devices and methods of forming the same. A semiconductor memory device is provided. The semiconductor memory device includes a memory cell having a first electrode, a second electrode, a switching layer, and a via structure. The second electrode is adjacent to a side of the first electrode and the switching layer overlays uppermost surfaces of the first and second electrodes. The via structure is over the uppermost surface of the second electrode.

Semiconductor memory devices

A structure includes a photodetector including alternating p-type semiconductor layers and n-type semiconductor layers in contact with each other in a stack. Each semiconductor layer includes an extension extending beyond an end of an adjacent semiconductor layer of the alternating p-type semiconductor layers and n-type semiconductor layers. The extensions provide an area for operative coupling to a contact. The extensions can be arranged in a cascading, staircase arrangement, or may extend from n-type semiconductor layers on one side of the stack and from p-type semiconductor layers on another side of the stack. The photodetector can be on a substrate in a first region, and a complementary metal-oxide semiconductor (CMOS) device may be on the substrate on a second region separated from the first region by a trench isolation. The photodetector is capable of detecting and converting near-infrared (NIR) light, e.g., having wavelengths of greater than 0.75 micrometers.

Multi-semiconductor layer photodetector and related method

The present disclosure relates to sensors and, more particularly, to magnetic field sensors. More specifically, a structure includes a package with a wraparound geometry and discontinuous ends, and includes a low permeability magnetic material.

Magnetic field sensor

Growing community of inventors

Singapore, Singapore

Eng Huat Toh