Intel Corporation

Other

Eng Huat Goh

Min Suet Lim

Jiun Hann Sir

Khang Choong Yong

Tin Poay Chuah

Wil Choon Song

Hoay Tien Teoh

Jackson Chung Peng Kong

Bok Eng Cheah

Boon Ping Koh

Poh Boon Khoo

Debendra Mallik

Amruthavalli Pallavi Alur

Ping Ping Ooi

Yew San Lim

Jia Yan Go

Howe Yin Loo

Khai Ern See

Wee Hoe

Mohd Muhaiyiddin Bin Abdullah

Chee Ling Wong

Kooi Chi Ooi

Jenny Shio Yin Ong

Seok Ling Lim

Chin Lee Kuan

Mooi Ling Chang

Cheng Siew Tay

Fern Nee Tan

Swee Kian Cheng

Han Kung Chua

Teong Keat Beh

Jimmy Huat Since Huang

Shawna M Liff

Feras Eid

Telesphor Kamgaing

Robert L Sankman

Amit Kumar Srivastava

Md Altaf Hossain

Chee How Lim

Jimin Yao

Stephen H Hall, Jr

Richard Christopher Stamey

Poh Tat Oh

Su Sin Florence Phun

Teong Guan Yew

Jenn Chuan Cheng

Mark A Schaecher

Chee Chun Yee

Twan Sing Loo

Xi Guo

Paik Wen Ong

Min Keen Tang

Chu Aun Lim

Say Thong Tony Tan

Kevin Byrd

James Wade

J-Wing Teh

Kean Huat Leong

Chun Kit See

Sheng Jian Darren Tan

Damien Weng Kong Chong

Siew Fong Yap

Jon Sern Lim

Chee Kheong Yoon

Kyle Davidson

An embedded multi-die interconnect bridge (EMIB) is fabricated on a substrate using photolithographic techniques, and the EMIB is separated from the substrate and placed on the penultimate layer of an integrated-circuit package substrate, below the top solder-resist layer. A low Z-height of the EMIB, allows for useful trace and via real estate below the EMIB, to be employed in the package substrate.

Stripped redistrubution-layer fabrication for package-top embedded multi-die interconnect bridge

In one embodiment, a system includes a first circuit defining recesses along an edge of the first circuit board, and a second circuit board defining fins extending from at least one outer edge of the second circuit board. The fins of the second circuit board are positioned within the recesses of the second circuit board to connect the circuit boards in a co-planar manner. The fins and recesses may be shaped to provide an interlocking connection of the first and second circuit boards in the co-planar direction.

Co-planar interconnection mechanisms for circuit boards

An integrated circuit package may be fabricated by disposing an underfill material between an electronic substrate and an integrated circuit device through an opening in the electronic substrate. In one embodiment, an integrated circuit assembly may include an electronic substrate having a first surface and an opposing second surface, wherein the electronic substrate includes at least one opening extending from the first surface to the second surface. The integrated circuit assembly may further include an integrated circuit device, wherein the integrated circuit device is electrically attached to the electronic substrate with at least one interconnect, and an underfill material may be disposed between the first surface of the electronic substrate and the integrated circuit device, wherein a portion of the underfill material extends into the opening in the electronic substrate.

Through-substrate underfill formation for an integrated circuit assembly

Methods and apparatus relating to integrating System in Package (SiP) with Input/Output (IO) board for platform miniaturization are described. In an embodiment, a SiP board includes a plurality of logic components. An IO board is coupled to the SiP board via a grid array. The plurality of logic components is provided on both sides of the SiP board and one or more of the plurality of logic components are to positioned in an opening in the IO board. Other embodiments are also disclosed and claimed.

Integrating system in package (SiP) with input/output (IO) board for platform miniaturization

A semiconductor package is disclosed, which comprises a substrate, one or more dies on a first side of the substrate, and a plurality of interconnect structures having a first pitch and coupled to a second side of the substrate. The interconnect structures may attach the substrate to a board. The substrate may include a first interconnect layer having a second pitch. The first interconnect layer may be coupled to the one or more dies through second one or more interconnect layers. Third one or more interconnect layers between the first interconnect layer and the interconnect structures may translate the first pitch to the second pitch. The substrate may include a recess on a section of the second side of the substrate. The semiconductor package may further include one or more components within the recess and attached to the second side of the substrate.

Multi-use package architecture

In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing a Pad on Solder Mask (PoSM) semiconductor substrate package. For instance, in accordance with one embodiment, there is a substrate package having embodied therein a functional silicon die at a top layer of the substrate package; a solder resist layer beneath the functional silicon die of the substrate package; a plurality of die bumps at a bottom surface of the functional silicon die, the plurality of die bumps electrically interfacing the functional silicon die to a substrate through a plurality of solder balls at a top surface of the solder resist layer; each of the plurality of die bumps electrically interfaced to a nickel pad at least partially within the solder resist layer and beneath the solder balls; each of the plurality of die bumps electrically interfaced through the nickel pads to a conductive pad exposed at a bottom surface of the solder resist layer; and in which each of the conductive pads exposed at the bottom surface of the solder resist layer are electrically interfaced to an electrical trace at the substrate of the substrate package. Other related embodiments are disclosed.

Systems and apparatuses for implementing a pad on solder mask (POSM) semiconductor substrate package

A molded frame interconnect includes power, ground and signal frame interconnects in a molded mass, that encloses an integrated-circuit package precursor, which is inserted into the frame, and coupled to the frame interconnects by a build-up redistribution layer.

Organic mold interconnects in shielded interconnects frames for integrated-circuit packages

According to the various aspects, the present device includes a printed circuit board having a top surface and a bottom surface, with a plurality of semiconductor devices coupled to the top surface and a flexible electromagnetic shield wrap conformally positioned over and between the plurality of semiconductor devices and the top surface of the printed circuit board. The flexible electromagnetic shield wrap is conformally positioned by applying a vacuum and is removable after the vacuum seal is broken.

Wrappable EMI shields

Disclosed embodiments include die-edge level passive devices for integrated-circuit device packages that provide a low-loss path to active and passive devices, by minimizing inductive loops.

Reverse-bridge multi-die interconnect for integrated-circuit packages

Embodiments include semiconductor packages and method of forming the semiconductor packages. A semiconductor package includes a package substrate on a substrate, a die on the package substrate, and a conductive stiffener over the package substrate and the substrate. The conductive stiffener surrounds the package substrate, where the conductive stiffener has a top portion and a plurality of sidewalls, and where the top portion is directly disposed on the package substrate, and the sidewalls are vertically disposed on the substrate. The semiconductor package also includes the substrate that has a plurality of conductive pads, where the conductive pads are conductively coupled to a ground source. The conductive stiffener may conductively couple the package substrate to the conductive pads of the substrate. The top portion may have a cavity that surrounds the die, where the top portion is directly disposed on a plurality of outer edges of the package substrate.

RFI free picture frame metal stiffener

Embodiments disclose electronic packages with a die assembly and methods of forming such electronic packages. In an embodiment, a die assembly comprises a first die and a second die laterally adjacent to the first die. In an embodiment, the first die and the second die each comprise a first semiconductor layer, an insulator layer over the first semiconductor layer, and a second semiconductor layer over the insulator layer. In an embodiment, a cavity is disposed through the second semiconductor layer. In an embodiment, the die assembly further comprises a bridge substrate that electrically couples the first die to the second die, where the bridge is positioned in the cavity of the first die and the cavity of the second die.

Disaggregated die interconnection with on-silicon cavity bridge

Electronic device package on package (POP) technology is disclosed. A POP can comprise a first electronic device package including a heat source. The POP can also comprise a second electronic device package disposed on the first electronic device package. The second electronic device package can include a substrate having a heat transfer portion proximate the heat source that facilitates heat transfer from the heat source through a thickness of the substrate. The substrate can also have an electronic component portion at least partially about the heat transfer portion that facilitates electrical communication. In addition, the POP can comprise an electronic component operably coupled to the electronic component portion.

Electronic device package on package (POP)

A multilayer printed circuit board including a first printed circuit board portion, including a first inserting connector, including a plurality of contacts for creating a first removable bus connection; a second printed circuit board portion, including a second inserting connector, including a plurality of contacts for creating a second removable bus connection; a third printed circuit board portion, connected between the first printed circuit board portion and to the second printed circuit board portion, wherein a rigidity of the third printed circuit board portion is less than a rigidity of each of the first printed circuit board portion and the second printed circuit board portion; wherein the multilayer printed circuit board is foldable along the third printed circuit board portion and, if so folded, the first printed circuit board portion is arranged on top of the second printed circuit board portion.

System in package dual connector

Growing community of inventors

Penang, Malaysia

Eng Huat Goh