Chartered Semiconductor Manufacturing Ltd (Corporation)

Other

National University of Singapore

Nanyang Technological University

Institute of Microelectronics

Eng Fong Chor

Chung Foong Tan

Cher Liang Cha

Lap Chan

Jinping Liu

Shiang Yang Ong

Bangun Indajang

Hyeok Jae Lee

Elgin Kiok Quek

Anqing Zhang

Teck Koon Lee

Hyeokjae Lee

Hao Gong

Gong Hao

Zhifeng Joseph Xie

A method for incorporating carbon into a wafer at the interstitial a-c silicon interface of the halo doping profile is achieved. A bulk silicon substrate is provided. A carbon-doped silicon layer is deposited on the bulk silicon substrate. An epitaxial silicon layer is grown overlying the carbon-doped silicon layer to provide a starting wafer for the integrated circuit device fabrication. An integrated circuit device is fabricated on the starting wafer by the following steps. A gate electrode is formed on the starting wafer. LDD and source and drain regions are implanted in the starting wafer adjacent to the gate electrode. Indium is implanted to form halo implants adjacent to the LDD regions and underlying the gate electrode wherein the halo implants extend to an interface between the epitaxial silicon layer and the carbon-doped silicon layer wherein carbon ions in the carbon-doped silicon layer act as a silicon interstitial sink for silicon interstitials formed by the halo implants to prevent end of range secondary defect formation.

End of range (EOR) secondary defect engineering using chemical vapor deposition (CVD) substitutional carbon doping

End of range (EOR) secondary defect engineering using substitutional carbon doping

A pocket implant process to reduce defects. We provide a gate structure, on a semiconductor substrate doped with a first conductivity type dopant. We perform a pocket amorphizing implantation procedure to form a pocket implant region adjacent to the gate structure, and an amorphous pocket region. Next, we perform a shallow amorphizing implant to form an amorphous shallow implant region. The amorphous shallow implant region being formed at a second depth above the amorphous pocket region. The substrate above the amorphous shallow implant region preferably remains crystalline. We perform a S/D implant procedure to form Deep S/D regions. We perform an anneal procedure preferably comprised of a first soak step and a second spike step to recrystalilze the amorphous shallow implant region and the amorphous pocket region, The defects created by the pocket implant are reduced by the shallow amorphous implant.

Shallow amorphizing implant for gettering of deep secondary end of range defects

Formation of a MOSFET with a polysilicon gate electrode embedded within a silicon trench is described. The MOSFET retains all the features of conventional MOSFETs with photolithographically patterned polysilicon gate electrodes, including robust LDD (lightly doped drain) regions formed in along the walls of the trench. Because the gate dielectric is never exposed to plasma etching or aqueous chemical etching, gate dielectric films of under 100 Angstroms may be formed without defects. The problems of over etching, and substrate spiking which are encountered in the manufacture of photolithographically patterned polysilicon gate electrodes do not occur. The entire process utilizes only two photolithographic steps. The first step defines the silicon active area by patterning a field isolation and the second defines a trench within the active area wherein the device is formed. The new process, uses the same total number of photolithographic steps to form the MOSFET device elements as a conventional process but is far more protective of the thin gate oxide.

Embedded polysilicon gate MOSFET

This invention relates to the new reversed flash memory device which has improved electrical performance, yield and reliability because of better control of the dielectric interfaces resulting from first making the poly 2 control gate within the silicon substrate. The reverse structure is novel, as are the described process methods for forming the reverse stacking order. Shallow trenched isolation (STI) is first formed in the p-silicon substrate and encompasses the poly 2 control gate region; then the interpoly dielectric is grown/deposited on that single crystal silicon substrate. The floating poly 1 is formed on top of this uniform interpoly dielectric that has well-controlled surface smoothness. The tunnel oxide layer is formed on the floating poly 1 layer, and the source/drain is implanted on a straddling additional poly layer. There are fewer edges and associated stress weaknesses in the dielectric breakdown of both the reversed interpoly dielectric and the floating tunnel oxide. The results are improved electrical quality and more acceptable electrical parameters, including reversed flash memory devices with gate length dimensions below 0.35 microns.

Production of reversed flash memory device

Small metallic patches embedded in a mainly non-metallic surface may be detected and mapped by placing a wire coil at the free end of a cantilever, with a fine tip made of a ferro-magnetic material located at its center. An alternating current is passed through the coil so that when it is near a metallic patch eddy currents are induced in the patch. These produce a small magnetic moment in the patch which pulls the tip towards the surface. This movement of the tip is detected by observing a light beam that is reflected off the surface of the cantilever. By plotting the output of a photodetector, sensistive to small changes in the reflected beam's position, as a function of the tip's location over the surface, a map of the metallic patches is produced.

Method and apparatus to image metallic patches embedded in a non-metal

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Singapore, Singapore

Eng Fong Chor