International Business Machines Corporation

Endre P Thoma

Robert E Busch

Alfred L Sartwell

Theodore M Redman

Steven Michael Eustis

Wayne Frederick Ellis

Erik L Hedberg

Dale E Pontius

Edward Butler

John B DeForge

David E Douse

Michael A Roberge

Susan M Litten

William Paul Hovis

Minh H Tong

Frederick J Aichelmann, Jr

Francis H Chan

Robert Tamlyn

John A Gabric

Bruce E Bachman

James A Yankosky

Ronald A Sasaki

Cheryl Jean Herdey

Eric Stephen Machat

Electrical mask identification of memory modules

An integrated semiconductor module of reduced impedance and method utilizing a given chip architecture of the type having a memory circuit and a plurality of off-chip drivers and their I/O pads, the module being constructed in a configuration for operation of said memory circuit with less than the number of available drivers such that there are a number of excess drivers and output pads not used for driver operations, and one or more of these excess drivers and their pads are connected to the power terminals of the chip to provide one or more power paths through these drivers and their associated pads in parallel with the power paths of the operational drivers, and the method includes connecting the excess drivers and their output pads to the power terminals of the chip during its fabrication in a manner to provide additional power paths.

Integrated circuit module having reduced impedance and method of providing the same

An off-chip driver (OCD) circuit including a clamp circuit to limit overdrive is provided. The circuit comprises an input signal which is inverted to provide an output signal. The driver circuit is comprised of a source-follower transistor to pull-down the output signal. The clamp circuit actively feeds back the source-follower potential to slow down the OCD and minimize ground bounce and noise that causes circuits to fail and signal integrity to be corrupted. The simple drive and clamp circuit is comprised of three transistors, one resistor, and one capacitor. The OCD slew rate is controlled by a current source and provides an output that changes between a positive voltage and ground. The circuit limits dv/dt without using a large resistor as a source follower, hence minimizing the adverse effect on performance.

Clamp circuit to limit overdrive of off chip driver

A Random Access Memory including a redundancy scheme wherein redundant memory elements are organized in a mixture of redundancy patches of various sizes, i.e., various number of word/ bit lines in each patch. The number of lines, e.g., 1, 2, 4 or 8 word or bit lines, in each of the patches is selected as appropriate with many different sized patches existing within the same redundancy reservoir. The size the particular patch selected depends on the size of the replaced defect detected during programming.

Multiple repair size redundancy

The present invention provides an apparatus and method for monitoring the functioning of a special operational mode on an integrated circuit module without the need for a special or dedicated pin. By monitoring the data output pins of the module operation in a special operational mode and premature interruption thereof, is detected. Delayed transition from a state of low impedance to a state of high impedance during the data output cycle is indicative of the special operational mode. The modules which usually have tri-state devices on their output lines are provided with delay circuitry to delay the transition of the tri-state device, during the data output cycle, from a state of low impedance to a state of high impedance while the device remains in a special operating mode.

Data output impedance control

In one aspect a memory bank selection system includes two asynchronous RAS pins and a single CAS pin, a switching circuit for each memory bank and a bank address decoder with an output to each switching circuit. The RAS pins are available to all of the switching circuits. A given switching circuit selects its associated bank if an active RAS signal is present and the bank address decoder output was sent thereto. The number of memory banks that can be simultaneously active directly depends on the number of RAS inputs. In another aspect, the number of CAS pins is equal to the number of asynchronous RAS pins.

Method and apparatus for multiple memory bank selection

A multimedia dynamic random-access memory (DRAM) or video random-access memory (VRAM) having enhanced block overwrite capabilities includes a plurality of sense amplifiers which are selectively coupled to an array of memory cells via paired bit lines for sensing/writing charge to the memory cells. Each sense amplifier is controlled by a primary set device and a secondary set device. The secondary set device is of smaller size than the primary set device but still sized sufficiently to maintain accessed data appearing on the paired bit lines. Upon decoding of a block overwrite request, the primary set device is momentarily turned off to facilitate forcible overwriting of selected sense amplifiers with new data while the secondary set device maintains data appearing on unselected sense amplifiers. Once block overwrite is complete, the primary set device is reactivated and charge is restored to the memory cells. By momentarily deactivating the primary set device, block overwriting of a large number of bit line pairs is possible.

Semiconductor memory circuit with block overwrite

A memory chip, comprising a chip memory section organized to hold a plurality of separate blocks of data, with each of the data blocks containing M individual data units; a circuit for addressing a given block of data in the chip memory section; and an N data unit chip parallel output interface from the memory chip where N is less than M, and N is greater than one. The memory chip further comprises a chip register for receiving from the chip memory section at least a portion of an addressed block of data, which portion comprises P data units, where P is greater than N, the chip register having P register stages for holding the P data units of the addressed data block, wherein the P register stages are grouped into at least a first and second groups of stages, with no group of stages comprising more than N register stages and with at least one of the groups of register stages having a plurality of stages. The memory chip also includes a gating structure for gating the respective groups of stages to the N data unit parallel output interface, the gating structure including at least a first gate circuit for gating in parallel the data units held in the first group of stages to the N data unit parallel output interface in accordance with a TOGGLE logic signal, and a second gate circuit for gating in parallel the data units held in the second group of stages to the N data unit parallel output interface in accordance with a NOT TOGGLE logic signal.

Fast access memory structure

A signal margin testing system is provided for a memory having a word line voltage boosting circuit which uses a test mode decode circuit to selectively disable the word line boosting circuit and then read out data from storage cells in the memory.

Signal margin testing system for dynamic RAM

A method and device for setting at least three operating modes of a memory device is provided. The voltage signal is sensed at a first input and an enable signal is sensed at a second input. When an enable signal is received at a second input the memory device operates at the first operating mode if the voltage state at the first input is low; it operates at a second mode if the voltage state at the second is high; and it operates at a third operating mode if the voltage at the first input changes after the enable signal is received at the input. Also a four mode operation can be achieved.

Multiple mode-set for IC chip

A memory device which includes several partially defective memory chips and a control circuit for receiving an address signal corresponding to a storage cell address of each of the partially defective memory chips, and for controlling, in response to the address signal, the partially defective memory chips such that only one thereof is enabled.

Memory module utilizing partially defective memory chips

An improved voltage regulator system is provided which includes a differential amplifier, an output transistor having a control electrode coupled to an output of the differential amplifier and a current carrying electrode fed back to an input of the amplifier, an input control transistor having a first current carrying electrode connected to the control electrode of the output transistor and a second current carrying electrode connected to a point of fixed potential and means for selectively applying a control signal to a control electrode of the input control transistor.

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Colchester, VT, United States of America

Endre P Thoma