National Taiwan University

Industrial Technology Research Institute

Enboa Wu

Shou-Lung Chen

Hsin-Chien Huang

Tsung-Yao Chu

Rou-Ching Yang

Chia-Shou Chang

Ying-Ching Shih

Rong-Shen Lee

Chung-Tao Chang

Kuo-Ching San

Xing-Xiang Liu

A method for self-assembling a plurality of microstructures onto a substrate comprising using a bonding material to make the microstructure assembled onto the substrate by a physical attraction force. The microstructures are self-aligned with the substrate, and further permanently fixed on and electrical connection with the substrate by the solder bumps between the microstructures and the substrate, which is formed by the solder bumps via reflow process. There is no need for the using of the conventional pick-and-place device in the present method. The present method could be applied to light emitting diodes, RFID tags, micro-integrated circuits or other types of microstructures.

Method for self-assembling microstructures

A thermal enhanced low profile package structure and a method for fabricating the same are provided. The package structure typically includes a metallization layer with an electronic component thereon which is between two provided dielectric layers. The metallization layer as well as the electronic component is embedded and packaged while the substrates are laminated via a lamination process. The fabricated package structure performs not only a superior electric performance, but also an excellent enhancement in thermal dissipation.

Thermal enhanced low profile package structure and method for fabricating the same

Thermal enhanced low profile package structure

A method for wafer level package (WLP) of sensor chips is provided, including the steps of: providing a wafer, the wafer including a plurality of die regions, each the die region on a first surface of the wafer comprising an active area and a pad surrounding the active area; bounding a transparent protective layer to the first surface of the wafer; forming a stress buffer on a second surface of the wafer; using etching or laser drill to form a via hole at the location between two neighboring die regions through the stress buffer and the wafer to expose the pad or a conductive line between two neighboring pads; and forming a plurality of bump electrodes on the stress buffer for electrical connection to the pads through the via holes. The method can prevent pollution of the die, improve the convenience of package, reduce the manufacture cost, increase the package reliability, and solve the stress problem caused by attaching the die directly to the PCB.

Method for wafer level package of sensor chip

A light emitting diode (LED) covered with a reflective layer by imprinting process is provided. The imprinting process includes coating a plastic layer on a mold to form an imprinting substrate; coating a reflective layer on the plastic layer and modifying the shape of the reflective layer to fit the shape of outer surfaces of the light emitting diode; softening the plastic layer and impressing the mold covered with the reflective layer upon the LED structure so that the reflective layer adheres to the surfaces of LED; and removing the mold. Because the reflective layer has high reflectivity, the light emitted from the top surface and side surfaces of LED is reflected back to the light extraction direction, and thereby the light extraction efficiency is enhanced.

Light emitting diode covered with a reflective layer and method for fabricating the same

A transceiver module comprised of a multiplexing/demultiplexing optical subassembly is provided. The optical subassembly includes either a transmitter module or a receiver module or both. The transmitter module has laser diodes emitting optical signals, which are reflected by reflectors, and coupled together by thin film filter. The receiver module includes thin film filters that decouple a received optical signal into constituent components. These components are reflected by reflectors to photo detectors by which the optical signals are converted into electrical signals. The reflector are capable of dual axis adjustment for adjustment of inclination thereof to effect active alignment. Further, the transmitter module and the receiver module define positioning recesses to position the laser diodes and photo detectors. The recesses are sized in accordance with the wavelengths associated with the laser diodes and photo detectors to effect passive alignment.

Optical subassembly of optical transceiver

The invention discloses a tunable long period fiber grating structure and fabrication method, which produces an expected microbending deformation by adjusting the temperature and making use of the unmatched coefficients of thermal expansion between different materials, and thus creating a phenomenon of mode coupling effect occurred in traditional optical gratings in order to provide the structure and fabrication method for having an effect of tuning spectra by controlling the temperature. This invention not only can be applied to the optical communications and wavelength dependent multiplexed devices and equipments, but also can be applied to the temperature and deformation detection. The tunable long period fiber grating structure in accordance to the present invention comprises a substrate; a periodic structure being disposed thereon and having a first coefficient of thermal expansion; a coupling agent, having a second coefficient of thermal expansion for fixing a fiber to the periodic structure; wherein the first and second coefficients of thermal expansion are different.

Tunable long period fiber grating structure and fabrication method

A single-step bumping/bonding method for forming a semiconductor package of two electronic substrates electrically connected together by solder bumps. In the method, a first electronic substrate is provided equipped with a first plurality of conductive pads formed in an insulating material layer, the plurality of conductive pads each having an aperture formed therethrough for receiving a solder material when the first electronic substrate is positioned juxtaposed to a second electronic substrate equipped with a second plurality of conductive pads such that solder bumps may be formed bonding the first plurality of conductive pads to the second plurality of conductive pads. One of the two electronic substrates may be a silicon wafer, while the other may be a printed circuit board or a silicon wafer.

Electronic substrate having an aperture position through a substrate, conductive pads, and an insulating layer

A wafer level package that incorporates dual stress buffer layers for achieving I/O pad redistribution and a method for forming the package are disclosed. In the package, a first stress buffer layer and a second stress buffer layer are sequentially deposited on top of an IC die by a method such as spin coating, laminating, screen printing or stencil printing of an elastic material which has a Young's modulus of less than 10 MPa. A suitable thickness for the first and the second stress buffer layer is between about 10 &mgr;m and about 70 &mgr;m. Metal traces are formed on top of the first and the second stress buffer layer for connecting a first plurality of I/O pads and a second plurality of I/O pads to achieve I/O redistribution.

Growing community of inventors

Taipei, Taiwan

Enboa Wu