Hefei Core Storage Electronic Limited

En Yang Wang

Chih-Ling Wang

Kuai Cao

Dong Dong Yao

Yun Zhang

Wen Qing Lv

Ya Jie Guo

A memory management method, a memory storage device, and a memory control circuit unit are provided. The memory management method includes: creating a physical block management table for managing physical blocks; selecting at least one physical block to be refreshed based on the physical block management table when power is restored after an abnormal power loss; in response to a number of the at least one physical block to be refreshed being greater than 1, determining at least one current state and at least one category of the at least one physical block to be refreshed; and executing at least one second write operation based on the current state and the category together when executing a first write operation. The first write operation includes writing user data into a cache. The second write operation includes writing data stored in a physical block to be refreshed into a first physical block.

Memory management method for evenly distributing input output latency time, memory storage device, and memory control circuit unit

A data writing method, a memory storage device, and a memory control circuit unit are provided. The data writing method includes the following: calculating a first number according to a ratio of a capacity of at least one first system table to a capacity of a physical block; calculating a second number according to a ratio of a capacity of at least one second system table to the capacity of the physical block; and obtaining at least one physical block from a plurality of physical blocks as a first virtual block and a second virtual block based on the first number and the second number respectively.

Data writing method, memory storage device and memory control circuit unit

A performance match method of memory, a memory storage device and a memory control circuit unit are disclosed. The method includes: receiving a performance match command from a host system; in response to the performance match command, adjusting an operation setting of a memory storage device to match a performance of the memory storage device with a performance requirement of the host system; and interacting with the host system based on the adjusted operation setting.

Performance match method of memory, memory storage device and memory control circuit unit

A mapping table updating method, a memory storage device and a memory control circuit unit are disclosed. The method includes: receiving, a plurality of operation commands from a host system; performing a first table updating operation according to a first operation command and a third operation command among the operation commands to read and update a first sub-mapping table and a third sub-mapping table from a rewritable non-volatile memory module; and after the first table updating operation is finished, performing a second table updating operation according to a second operation command among the operation commands to read and update a second sub-mapping table from the rewritable non-volatile memory module.

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Anhui, China

En Yang Wang