Sun Microsystems, Inc.

Oracle America, Inc.

Emrys John Williams

Paul Jeffrey Garnett

Stephen Rowlinson

Femi A Oyelakin

Robert Cypher

Drew George Doblar

Martin Paul Mayhead

Leo Yuan

Andrew Crosland

A memory system including independent power for each memory module. The memory system includes a plurality of memory modules each including a plurality of memory chips configured to store data. The memory system further includes a power conversion unit coupled to provide power to each of the plurality of memory modules via a respective power conduit. Each of the respective power conduits is electrically isolated from each other power conduit.

Memory system including independent isolated power for each memory module

One embodiment of the invention provides apparatus and a method for testing a transmission path across one or more printed circuit boards. According to the method, a test signal is presented at a first location on the transmission path. The test signal is generally low frequency compared to normal data communications on the transmission path. A pickup line is capacitively coupled at a second location to the transmission path. The pickup line is monitored with a detector to see whether or not the test signal is present. If the test signal is not present, it is determined that there is a fault on the transmission path between the first location and the second location.

Method and apparatus for testing a transmission path

A multiprocessor computer system which provides fault tolerance includes a number of processing sets. At least one of the processing sets is operable asynchronously of a second processing set. A monitor is connected to receive I/O operations output from the processing sets for identifying faulty operation of those units. The monitor is also operable to synchronise operation of the processing sets by signalling the processing sets on receipt of outputs from those units indicative of a plurality of them being at an equivalent stage of processing. The monitor provides for buffering of I/O operations output from the processing sets and for selective forwarding of those I/O operations to an external I/O bus. The processing set may be formed from a single processor or from multiple processors.

Determinism in a multiprocessor computer system and monitor and processor therefor

The invention relates to performing a service operation on a computer. In one embodiment, information indicative of the need for a service operation is sent by a customer computer to a support center. Based on this received information, the support center then identifies the service operation to be performed on the computer, such as the replacement of a faulty component. The support center then creates a service task record describing this service operation, which is transmitted from the support center to a mobile computing device associated with an engineer who is to complete the service operation. This typically includes schedule information, detailing when and where the service operation is to be performed. When the engineer then arrives at the customer location, a direct communication link is established between the customer computer to be serviced and the mobile computing device, for example using an infrared link. Information transmitted over this link allows the mobile computing device and the customer computer to confirm with one another the details of the service operation to be performed, such as which particular component of the computer is to be replaced. This minimises the likelihood of mistakes being made during the service operation. Finally, a confirmation that the repair has been completed can be transmitted from the mobile computing device and/or the customer computer itself back to the support center.

Service operations on a computer system

A system and method for improving the isolation and diagnosis of hardware faults in a computing system wherein means are provided for indicating whether unusable data has previously triggered diagnosis of the hardware fault that caused the data to be unusable. If diagnosis has not been performed, the flag is not set. If diagnosis has already been performed, the flag is set. One embodiment comprises an interface which is used to convey data from one subsystem to another. When the interface receives data from the first subsystem, the data is examined to determine whether it contains an uncorrectable error (including missing data.) If the data contains an uncorrectable error, the interface examines the flag corresponding to the data to determine whether hardware fault diagnosis has already been initiated. If diagnosis has already been initiated, the data is passed to the second subsystem without initiating further diagnosis. If diagnosis has not been initiated, the interface initiates diagnosis and sets the flag to indicate that diagnosis has already been initiated. The data and corresponding flag are then passed to the second subsystem. If the data contains an uncorrectable error, data error handling procedures will be performed by the subsystem that requested the data, regardless of the value of the corresponding flag.

Mechanism to improve fault isolation and diagnosis in computers

A system for limiting security attacks on a computer system that operate by executing computer instructions embedded in data received from an external source. The system receives the data from the external source and performs a transformation on the data that causes any computer instructions encoded in the data to be unexecutable. After the data is transformed, the system stores the data in the computer system's memory. When the data is needed, the system retrieves the data and reverses the transformation. In this way, data from an external source is stored in memory in an unexecutable form, thereby making it impossible to execute malicious code embedded in the data. According to one aspect of the present invention, the data is transformed using a random number, so that the data can only be converted back to its original form with an inverse transformation using the same random number.

Method and apparatus for limiting security attacks via data copied into computer memory

A system and method for providing redundant, synchronized clocks in a computer system. Upon a failure of a master clock signal, the system switches over to a slave clock signal synchronized with the master clock signal. Switching logic is coupled to receive a first clock signal and a second clock signal. The switching logic selects either the first clock signal or the second clock signal as a local clock signal. The switching logic further monitors the first clock signal for a failure. If a failure is monitored, the switching logic accepts the second clock signal as the local clock signal in place of the first clock signal. One or more clock local loads operate according to the local clock signal. The switching logic may control the input to a phase locked loop (PLL) that provides the local clock signal to the local clock loads. The method includes a PLL synchronizing an output clock signal with the master clock signal. The output clock signal is used by at least one local clock load for timing. The switching logic monitors the master clock signal and the slave clock signal for a failure. Upon a failure of either the master clock signal or the slave clock signal, the switching logic notifies a system controller of the failure. Upon the failure of the first clock signal, the switching logic switches the second clock signal in place of the first clock signal as the master clock signal for the PLL, causes the second clock signal to fail-over and to take over as the master clock source to the PLL, and causes the second clock source to provide a reference control signal to the second clock source. Clock switching is automatic and does not interrupt or interfere with operation of the computer system.

Computer system including multiple clock sources and failover switching

A program controlled apparatus includes one or more units for executing a multiple process. A mutex ordering mechanism controls the ordering of mutex ownership to provide deterministic execution of the processes. A mutex processor monitors mutex registers for determining mutex ownership. The mutex registers can be configured as sets of mutex request registers and mutex release registers. The apparatus may include a single processor configured to execute multiple processes concurrently, or multiple processing units, each configured to execute one or more processes. A monitor unit which can monitor equivalent operation of the processing sets can also include the mutex ordering mechanism.

Control of multiple computer processes using a mutual exclusion primitive ordering mechanism

A system that automatically integrates a module into a computer system to replace a module that has failed. The system operates by detecting an insertion of the module into the computer system. In response to this insertion, the system reads information from the module in order to identify what type of module has been inserted into the computer system. If the newly inserted module cannot perform functions of the prior module, the system signals an error condition. The system additionally reads information from the module in order to determine if the module has failed since it was first shipped or last repaired. This information was originally written by this or another system upon detection of a failure. If the module has failed since it was first shipped or last repaired, the system signals an error condition. Finally, if no error condition is signaled, the system integrates the module into the computer system. In a variation on the above embodiment, this integration process involves running functional tests on the module, and loading configuration information into the module. Thus, the present invention speeds up the integration process by dispensing with the need to manually enter integration commands into the computer system. This creates fewer opportunities for error because a technician is not required to memorize integration commands and will not inadvertently enter the wrong commands. The present invention also encourages proper service practice by encouraging a technician to return a failed module to a service depot, instead of simply cycling the injection switch of a module to &ldquo;repair&rdquo; the unit.

Method and apparatus for automatically reintegrating a module into a computer system

A direct memory access (DMA) controller is provided for a computer system having a processor and a command buffer. The command buffer can be defined, for example, as a ring buffer in the main processor memory and can be directly accessible by the processor, for example over a bus. The DMA controller provides a head register and a tail register operable to hold a head pointer and a tail pointer for addressing the head and tail, respectively, of a sequence of direct memory access commands in the command buffer. The processor is able to store DMA commands in the command buffer. Subsequently, the DMA controller is able to access those DMA commands using the DMA tail pointer held locally in the DMA controller. The DMA controller is operable to compare the head and tail pointers, and to respond to non-equivalence thereof to use the tail pointer value to access direct memory access commands from the command buffer. The DMA controller is responsible for updating the tail pointer in the DMA controller in association with reading of a direct memory access command from a location in the command buffer. The processor is responsible for updating the head pointer in the DMA controller in association with the storing of DMA commands in the command buffer.

Method of controlling DMA command buffer for holding sequence of DMA commands with head and tail pointers

An I/O monitor includes an interface mechanism for connection between a processor and an I/O bus and an error signal modifier. The error signal modifier responds to an error signal from the I/O bus by substituting a determined response for passing to the processor. By returning a determined response to the processor, as opposed to the bus error signal, the need for bus error exception processing by the processor software is removed. The monitor determines a resource forming the source of the bus error and labels the resource as defective in a status register for the resource in the monitor. The monitor generates an interrupt when a resource is first labelled as defective. Subsequently, further access to the resource by the processor are handled by the monitor. The monitor responds to an I/O read operation to a resource labelled as defective to prevent the I/O read operation from being passed to the bus and to return a determined data response. It responds to an I/O write operation to a resource labelled as defective to discard the I/O write operation and to terminate with an acknowledgement as the determined response.

Bus error handling in a computer system

A multiprocessor computer system which provides fault tolerance includes a number of processing sets. At least one of the processing sets is operable asynchronously of a second processing set. A monitor is connected to receive I/O operations output from the processing sets for identifying faulty operation of those units. The monitor is also operable to synchronize operation of the processing sets by signalling the processing sets on receipt of outputs from those units indicative of a plurality of them being at an equivalent stage of processing. The common monitor can be operable to determine not only faulty operation of the processing sets, but also to synchronize those units by monitoring the I/O operations output from the units. The monitor provides for buffering of I/O operations output from the processing sets and for selective forwarding of those I/O operations to an external I/O bus. A processing set may be formed from a single processor, or may be formed from multiple symmetric processors. A mutex ordering scheme can be provided to ensure deterministic access by the individual processors of the processing sets to local resources.

I/O handling for a multiprocessor computer system

A module for a modular system includes requirement indicators defining features of a component required for the module to operate, capability indicators defining features provided by the module and ability indicators defining features of the component acceptable to the module. The combination of the requirements, compatibility and ability indicators provides a very flexible structure for indicating and testing requirements and capabilities in that it permits the designation of requirements, capabilities and the capability to accept inverted capabilities. A variable number of the requirement, capability and ability indicators can be provided to accommodate future requirements. Verification logic is operable to determine compatibility when defined relationships between the requirement, capability and ability indicators for the module and an interconnected component are met. One of the module and the component can be a system component such as a mother board.

Growing community of inventors

Sunnyvale, CA, United States of America

Emrys John Williams