Monterey Design Systems, Inc.

Emre Tuncer

Lawrence Thomas Pileggi

Douglas B Boyle

Sharad Malik

Abhijeet Chakraborty

James S Koford

Majid Sarrafzadeh

Salil Ravindra Raje

Christopher J Dunn

Gary K Yeap

Feroze P Taraporevala

David Gluss

Robert E Shortt

Lilly Shieh

Dennis Yamamoto

Tong Gao

Joseph T Rahmeh

Dinesh D Gaitonde

Satyamurthy Pullela

Eric McCaughrin

Altan Odabasioglu

Sam Jung Kim

Archie Li

Yau-Tsun Steven Li

Satamurthy Pullela

A design tool for integrated circuits includes a placement tool which concurrently places logic gates and interconnect. In one embodiment, the logic gates are placed into bins and virtual buffers are inserted between logic gates mapped to different bins. Placement and interconnect wire lengths and densities are successively improved leading to removal of some buffers and actualization of the virtual buffers.

System and method for concurrent buffer insertion and placement of logic gates

A method for design optimization using logical and physical information is provided. In one embodiment, a method for design optimization using logical and physical information, includes receiving a behavioral description of an integrated circuit or a portion of an integrated circuit, optimizing placement of circuit elements in accordance with a first cost function, and optimizing logic of the circuit elements in accordance with a second cost function, in which the optimizing placement of the circuit elements and the optimizing logic of the circuit elements are performed concurrently. The method can further include optimizing routing in accordance with a third cost function, in which the optimizing routing, the optimizing placement of the circuit elements, and the optimizing logic of the circuit elements are performed concurrently.

Method for design optimization using logical and physical information

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Palo Alto, CA, United States of America

Emre Tuncer