Arm Limited

Emre Ozer

Shidhartha Das

Xabier Iturbe

David Michael Bull

Balaji Venu

Mbou Eyole

John Philip Biggs

Jedrzej Kufel

James Edward Myers

Remy Pottier

Milosch Meriac

Stuart David Biles

Daniel Kershaw

Yiannakis Sazeides

Methods of performing post-manufacturing adaptation of a data processing apparatus manufactured in accordance with a processor design and corresponding data processing apparatus configurations are provided. Post-manufacturing testing of the data processing apparatus determines any dysfunctional instructions by comparison between component usage profiles for each instruction and a component fault-detection procedure applied to the data processing apparatus. The data processing apparatus can be determined nevertheless to be operationally viable when any dysfunctional instructions can be substituted for by emulation using other functional instructions. The data processing apparatus can be provided with dysfunctional instruction handling circuitry configured to identify occurrence of a program instruction instance of a dysfunctional instruction and to invoke an interrupt handling routine associated with the dysfunctional instruction to emulate the instance of a dysfunctional instruction.

Post-manufacturing adaptation of a data processing apparatus

A battery cell monitoring system comprises a flexible substrate able to conform to a surface of a battery cell to be monitored, and a plurality of first-level prediction units integrated onto the flexible substrate, where each first-level prediction unit is positioned at a different location on the flexible substrate to each other first-level prediction unit. Each first-level prediction unit comprises at least one sensor to generate sensor signals indicative of a physical state of the battery cell, and first-level prediction circuitry to generate a predicted battery cell status value in dependence on the sensor signals received from the at least one sensor of that first-level prediction unit. Second-level prediction circuitry is arranged to determine a prediction result in dependence on the predicted battery cell status values generated by the first-level prediction circuitry of each first-level prediction unit, and a communications device is used to output the prediction result at least when the prediction result indicates an occurrence of a critical event.

Technique for monitoring a battery cell

Wearable items and methods of monitoring wearable items are disclosed. The wearable item comprises a flexible base material forming at least a portion of the wearable item, plural conductive traces traversing the flexible base material, and conductivity sensing circuitry coupled to the plural conductive traces. The conductivity sensing circuitry is configured to distinguish conductivity from non-conductivity of the plural conductive traces, and configured to generate a conductivity indication for at least one of the plural conductive traces. The plural conductive traces follow indirect paths across the flexible base material, allowing the flexible material to flex and stretch normally without breaking the conductive traces.

Integrity monitoring for flexible material

A safety-based prediction apparatus, system and method are provided. A machine learning hardware accelerator (MLHA) includes a main classifier (MC) module, at least one guardian classifier (GC) module, and a final predicted class decision module. The MC module predicts an MC predicted class based on input data, and includes a pre-trained, machine learning main classifier (MLMC) that has at least one safety critical (SC) class and a plurality of non-SC classes. Each guardian classifier (GC) module is associated with an SC class, and predicts a GC predicted class based on the input data. Each GC module includes a pre-trained, machine learning guardian classifier (MLGC) having two classes including an associated SC class and a residual class that includes any non-associated SC classes and the plurality of non-SC classes. A decision module determines and outputs a final predicted class based on the MC predicted class and each GC predicted class.

Safety-based prediction apparatus, system and method

Briefly, example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, to determine indicators of potential errors in a multi-processing core lockstep computing device comprising a plurality of processing cores, based, at least in part, on observations of output signals generated by at least two processing cores of the plurality of processing cores. A built-in self-test (BIST) procedure may then be based, at least in part, on the determining indicators.

Device, system and process for redundant processor error detection

A method of reconfiguration and a reconfigurable circuit architecture comprising a configurable volatile storage circuit and Non-Volatile Memory circuit elements; wherein the Non-Volatile memory circuit elements store multiple bit states for re-configuration, the multiple bit states being read from the Non-Volatile memory circuit elements and written into the configurable volatile storage circuit for reconfiguration. The Non-Volatile Memory circuit elements and the configurable volatile storage circuit are provided on a common die.

Reconfigurable circuit architecture

Examples of the present disclosure relate to a method for anomaly response in a system on chip. The method comprises measuring a magnitude of a transient anomaly event in an operating condition of the system on chip. Based on the magnitude it is determined, for each of a plurality of components of the system on chip, an indication of susceptibility of that component to an anomaly event of the measured magnitude. Based on the determined indications of susceptibility for each of the plurality of components, an anomaly response action is determined. The method then comprises performing the anomaly response action.

Methods and apparatus for anomaly response

An apparatuscomprises at least three processing circuitsto perform redundant processing of a common thread of program instructions. Error detection circuitryis provided comprising a number of comparatorsfor detecting a mismatch between signals on corresponding signal nodesin the processing circuits. When a comparatordetects a mismatch, this triggers a recovery process. The error detection circuitrygenerates an unresolvable error signalindicating that a detected area is unresolvable by the recovery process when, during the recovery process, a mismatch is detected by one of the proper subsetof the comparators. By considering fewer comparatorsduring the recovery process than during normal operation, the chances of unrecoverable errors being detected can be reduced, increasing system availability.

Error detection triggering a recovery process that determines whether the error is resolvable

Disclosed are devices and methods for storing values, symbols, parameters or conditions in memory devices as states, and subsequently mapping detected states as values, symbols parameters or conditions. In one implementation write operations may place first and second memory elements in a particular impedance state selected from between a low impedance or conductive state and a high impedance or insulative state. The high impedance or insulative state represents a first binary value or symbol while the low high impedance or conductive state represents a second binary value or symbol. Subsequently detected impedance states of the first and second memory elements may be mapped to the second binary value or symbol responsive to either of the detected impedance states being the high impedance or insulative state and the second detected impedance state.

Method, system and device for error correction in reading memory devices

A data processing apparatus has a plurality of storage elements residing at different physical locations within the apparatus, and fault history circuitry for detecting local transient faults occurring in each storage element, and for maintaining global transient fault history data based on the detected local transient faults. Analysis circuitry monitors the global transient fault history data to determine, based on predetermined criteria, whether the global transient fault history data is indicative of random transient faults occurring within the data processing apparatus, or is indicative of a coordinated transient fault attack. The analysis circuitry is then configured to initiate a countermeasure action on determination of a coordinated transient fault attack. This provides a simple and effective mechanism for distinguishing between random transient faults that may naturally occur, and a coordinated transient fault attack that may be initiated in an attempt to circumvent the security of the data processing apparatus.

Data processing apparatus and method for analysing transient faults occurring within storage elements of the data processing apparatus

An integrated circuit is provided with error detection circuitry and error repair circuitry. Error tolerance circuitry is responsive to a control parameter to selectively disable the error repair circuitry. The control parameter is dependent on the processing performed within the circuit. For example, the control parameter may be generated in dependence upon the program instruction being executed, the output signal value which is in error, the previous behavior of the circuit or in other ways.

Integrated circuit with error repair and fault tolerance

A processoris responsive to a stream of program instructions to issue program instructions under control of scheduling circuitryto respective execution unitsfor execution. The execution unitscan include error detecting circuitryfor detecting a change in an output signal which occurs after the output signal has latched and during an error detecting period following the latching of the output signal. The scheduling circuitryis arranged so as to suppress issue of program instructions to an execution unit 24 having such error detecting circuitryon consecutive processing cycles.

Growing community of inventors

Buckden, United Kingdom

Emre Ozer